From: Peter Maydell Date: Thu, 5 Jun 2025 14:18:01 +0000 (+0100) Subject: hw/arm/mps2: Configure the AN500 CPU with 16 MPU regions X-Git-Tag: v10.1.0-rc0~50^2~1 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=cd38e638c43e4d5d3fd65dd4529c2e6153c9c408;p=thirdparty%2Fqemu.git hw/arm/mps2: Configure the AN500 CPU with 16 MPU regions The AN500 application note documents that it configures the Cortex-M7 CPU to have 16 MPU regions. We weren't doing this in our emulation, so the CPU had only the default 8 MPU regions. Set the mpu-ns-regions property to 16 for this board. This bug doesn't affect any of the other board types we model in this source file, because they all use either the Cortex-M3 or Cortex-M4. Those CPUs do not have an RTL configurable number of MPU regions, and always provide 8 regions if the MPU is built in. Cc: qemu-stable@nongnu.org Reported-by: Corentin GENDRE Signed-off-by: Peter Maydell Reviewed-by: Alex Bennée Message-id: 20250605141801.1083266-1-peter.maydell@linaro.org --- diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c index 58efb41e6db..bd378e360b0 100644 --- a/hw/arm/mps2.c +++ b/hw/arm/mps2.c @@ -224,7 +224,11 @@ static void mps2_common_init(MachineState *machine) switch (mmc->fpga_type) { case FPGA_AN385: case FPGA_AN386: + qdev_prop_set_uint32(armv7m, "num-irq", 32); + break; case FPGA_AN500: + /* The AN500 configures its Cortex-M7 with 16 MPU regions */ + qdev_prop_set_uint32(armv7m, "mpu-ns-regions", 16); qdev_prop_set_uint32(armv7m, "num-irq", 32); break; case FPGA_AN511: