From: André Draszik Date: Thu, 5 Feb 2026 22:01:57 +0000 (+0000) Subject: clk: samsung: gs101: harmonise symbol names (clock arrays) X-Git-Tag: v7.1-rc1~59^2^2^2~6 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=cdd94147fd72974eb1d118b1ba3b79e8df0ea716;p=thirdparty%2Fkernel%2Flinux.git clk: samsung: gs101: harmonise symbol names (clock arrays) Most symbols for the clock descriptions (arrays) don't have a cmu_ prefix and all symbols have a _clks suffix where appropriate. Update the few outliers to also fall into this same scheme for consistency. Signed-off-by: André Draszik Link: https://patch.msgid.link/20260205-clk-gs101-symbol-names-v1-1-a7d9a7a4d108@linaro.org Signed-off-by: Krzysztof Kozlowski --- diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c index 44a8ecd332fd..d2bcd3a9daf8 100644 --- a/drivers/clk/samsung/clk-gs101.c +++ b/drivers/clk/samsung/clk-gs101.c @@ -339,7 +339,7 @@ #define GENERALIO_ACD_CHANNEL_3 0x3f0c #define GENERALIO_ACD_MASK 0x3f14 -static const unsigned long cmu_top_clk_regs[] __initconst = { +static const unsigned long top_clk_regs[] __initconst = { PLL_LOCKTIME_PLL_SHARED0, PLL_LOCKTIME_PLL_SHARED1, PLL_LOCKTIME_PLL_SHARED2, @@ -638,7 +638,7 @@ static const unsigned long cmu_top_clk_regs[] __initconst = { GENERALIO_ACD_MASK, }; -static const struct samsung_pll_clock cmu_top_pll_clks[] __initconst = { +static const struct samsung_pll_clock top_pll_clks[] __initconst = { /* CMU_TOP_PURECLKCOMP */ PLL(pll_0517x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk", PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, @@ -952,7 +952,7 @@ PNAME(mout_cmu_cmuref_p) = { "mout_cmu_top_boost_option1", * For gates remove _UID _BLK _IPCLKPORT and _RSTNSYNC */ -static const struct samsung_mux_clock cmu_top_mux_clks[] __initconst = { +static const struct samsung_mux_clock top_mux_clks[] __initconst = { MUX(CLK_MOUT_PLL_SHARED0, "mout_pll_shared0", mout_pll_shared0_p, PLL_CON0_PLL_SHARED0, 4, 1), MUX(CLK_MOUT_PLL_SHARED1, "mout_pll_shared1", mout_pll_shared1_p, @@ -1108,7 +1108,7 @@ static const struct samsung_mux_clock cmu_top_mux_clks[] __initconst = { CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1), }; -static const struct samsung_div_clock cmu_top_div_clks[] __initconst = { +static const struct samsung_div_clock top_div_clks[] __initconst = { DIV(CLK_DOUT_CMU_BO_BUS, "dout_cmu_bo_bus", "gout_cmu_bo_bus", CLK_CON_DIV_CLKCMU_BO_BUS, 0, 4), DIV(CLK_DOUT_CMU_BUS0_BUS, "dout_cmu_bus0_bus", "gout_cmu_bus0_bus", @@ -1253,13 +1253,13 @@ static const struct samsung_div_clock cmu_top_div_clks[] __initconst = { "mout_pll_shared3", CLK_CON_DIV_PLL_SHARED3_DIV2, 0, 1), }; -static const struct samsung_fixed_factor_clock cmu_top_ffactor[] __initconst = { +static const struct samsung_fixed_factor_clock top_ffactor_clks[] __initconst = { FFACTOR(CLK_DOUT_CMU_HSI0_USBDPDBG, "dout_cmu_hsi0_usbdpdbg", "gout_cmu_hsi0_usbdpdbg", 1, 4, 0), FFACTOR(CLK_DOUT_CMU_OTP, "dout_cmu_otp", "oscclk", 1, 8, 0), }; -static const struct samsung_gate_clock cmu_top_gate_clks[] __initconst = { +static const struct samsung_gate_clock top_gate_clks[] __initconst = { GATE(CLK_GOUT_CMU_BUS0_BOOST, "gout_cmu_bus0_boost", "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_BUS0_BOOST, 21, 0, 0), GATE(CLK_GOUT_CMU_BUS1_BOOST, "gout_cmu_bus1_boost", @@ -1425,19 +1425,19 @@ static const struct samsung_gate_clock cmu_top_gate_clks[] __initconst = { }; static const struct samsung_cmu_info top_cmu_info __initconst = { - .pll_clks = cmu_top_pll_clks, - .nr_pll_clks = ARRAY_SIZE(cmu_top_pll_clks), - .mux_clks = cmu_top_mux_clks, - .nr_mux_clks = ARRAY_SIZE(cmu_top_mux_clks), - .div_clks = cmu_top_div_clks, - .nr_div_clks = ARRAY_SIZE(cmu_top_div_clks), - .fixed_factor_clks = cmu_top_ffactor, - .nr_fixed_factor_clks = ARRAY_SIZE(cmu_top_ffactor), - .gate_clks = cmu_top_gate_clks, - .nr_gate_clks = ARRAY_SIZE(cmu_top_gate_clks), + .pll_clks = top_pll_clks, + .nr_pll_clks = ARRAY_SIZE(top_pll_clks), + .mux_clks = top_mux_clks, + .nr_mux_clks = ARRAY_SIZE(top_mux_clks), + .div_clks = top_div_clks, + .nr_div_clks = ARRAY_SIZE(top_div_clks), + .fixed_factor_clks = top_ffactor_clks, + .nr_fixed_factor_clks = ARRAY_SIZE(top_ffactor_clks), + .gate_clks = top_gate_clks, + .nr_gate_clks = ARRAY_SIZE(top_gate_clks), .nr_clk_ids = CLKS_NR_TOP, - .clk_regs = cmu_top_clk_regs, - .nr_clk_regs = ARRAY_SIZE(cmu_top_clk_regs), + .clk_regs = top_clk_regs, + .nr_clk_regs = ARRAY_SIZE(top_clk_regs), .auto_clock_gate = true, .gate_dbg_offset = GS101_GATE_DBG_OFFSET, .option_offset = CMU_CMU_TOP_CONTROLLER_OPTION, @@ -2434,15 +2434,15 @@ PNAME(mout_hsi0_usb31drd_p) = { "fout_usb_pll", "dout_hsi0_usb31drd", "fout_usb_pll" }; -static const struct samsung_pll_rate_table cmu_hsi0_usb_pll_rates[] __initconst = { +static const struct samsung_pll_rate_table hsi0_usb_pll_rates[] __initconst = { PLL_35XX_RATE(24576000, 19200000, 150, 6, 5), { /* sentinel */ } }; -static const struct samsung_pll_clock cmu_hsi0_pll_clks[] __initconst = { +static const struct samsung_pll_clock hsi0_pll_clks[] __initconst = { PLL(pll_0518x, CLK_FOUT_USB_PLL, "fout_usb_pll", "oscclk", PLL_LOCKTIME_PLL_USB, PLL_CON3_PLL_USB, - cmu_hsi0_usb_pll_rates), + hsi0_usb_pll_rates), }; static const struct samsung_mux_clock hsi0_mux_clks[] __initconst = { @@ -2660,8 +2660,8 @@ static const struct samsung_fixed_rate_clock hsi0_fixed_clks[] __initconst = { }; static const struct samsung_cmu_info hsi0_cmu_info __initconst = { - .pll_clks = cmu_hsi0_pll_clks, - .nr_pll_clks = ARRAY_SIZE(cmu_hsi0_pll_clks), + .pll_clks = hsi0_pll_clks, + .nr_pll_clks = ARRAY_SIZE(hsi0_pll_clks), .mux_clks = hsi0_mux_clks, .nr_mux_clks = ARRAY_SIZE(hsi0_mux_clks), .div_clks = hsi0_div_clks, @@ -2791,7 +2791,7 @@ static const struct samsung_cmu_info hsi0_cmu_info __initconst = { #define QCH_CON_UFS_EMBD_QCH_FMP 0x3094 #define QUEUE_CTRL_REG_BLK_HSI2_CMU_HSI2 0x3c00 -static const unsigned long cmu_hsi2_clk_regs[] __initconst = { +static const unsigned long hsi2_clk_regs[] __initconst = { PLL_CON0_MUX_CLKCMU_HSI2_BUS_USER, PLL_CON1_MUX_CLKCMU_HSI2_BUS_USER, PLL_CON0_MUX_CLKCMU_HSI2_MMC_CARD_USER, @@ -3166,8 +3166,8 @@ static const struct samsung_cmu_info hsi2_cmu_info __initconst = { .gate_clks = hsi2_gate_clks, .nr_gate_clks = ARRAY_SIZE(hsi2_gate_clks), .nr_clk_ids = CLKS_NR_HSI2, - .clk_regs = cmu_hsi2_clk_regs, - .nr_clk_regs = ARRAY_SIZE(cmu_hsi2_clk_regs), + .clk_regs = hsi2_clk_regs, + .nr_clk_regs = ARRAY_SIZE(hsi2_clk_regs), .sysreg_clk_regs = dcrg_memclk_sysreg, .nr_sysreg_clk_regs = ARRAY_SIZE(dcrg_memclk_sysreg), .clk_name = "bus",