From: Greg Kroah-Hartman Date: Fri, 9 Jan 2026 10:43:27 +0000 (+0100) Subject: drop soc-rockchp patch X-Git-Tag: v6.1.160~16 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=ce0af8fb3d19aabbed57063358a60201c2ea45d9;p=thirdparty%2Fkernel%2Fstable-queue.git drop soc-rockchp patch --- diff --git a/queue-5.10/pmdomain-use-device_get_match_data.patch b/queue-5.10/pmdomain-use-device_get_match_data.patch index d7aba502a0..ab68044906 100644 --- a/queue-5.10/pmdomain-use-device_get_match_data.patch +++ b/queue-5.10/pmdomain-use-device_get_match_data.patch @@ -94,10 +94,10 @@ Signed-off-by: Greg Kroah-Hartman void __iomem *base; --- a/drivers/soc/rockchip/pm_domains.c +++ b/drivers/soc/rockchip/pm_domains.c -@@ -9,11 +9,13 @@ +@@ -8,11 +8,13 @@ + #include #include #include - #include +#include #include #include @@ -109,7 +109,7 @@ Signed-off-by: Greg Kroah-Hartman #include #include #include -@@ -728,7 +730,6 @@ static int rockchip_pm_domain_probe(stru +@@ -623,7 +625,6 @@ static int rockchip_pm_domain_probe(stru struct device_node *node; struct device *parent; struct rockchip_pmu *pmu; @@ -117,7 +117,7 @@ Signed-off-by: Greg Kroah-Hartman const struct rockchip_pmu_info *pmu_info; int error; -@@ -737,13 +738,7 @@ static int rockchip_pm_domain_probe(stru +@@ -632,13 +633,7 @@ static int rockchip_pm_domain_probe(stru return -ENODEV; } diff --git a/queue-5.10/series b/queue-5.10/series index 6ca1945f67..3fbdd56997 100644 --- a/queue-5.10/series +++ b/queue-5.10/series @@ -387,7 +387,6 @@ powerpc-pseries-cmm-adjust-balloon_migrate-when-migrating-pages.patch media-mediatek-vcodec-fix-a-reference-leak-in-mtk_vcodec_fw_vpu_init.patch media-vpif_capture-fix-section-mismatch.patch media-samsung-exynos4-is-fix-potential-abba-deadlock-on-init.patch -soc-rockchip-power-domain-manage-resource-conflicts-with-firmware.patch pmdomain-use-device_get_match_data.patch pmdomain-imx-fix-reference-count-leak-in-imx_gpc_probe.patch lockd-fix-vfs_test_lock-calls.patch diff --git a/queue-5.10/soc-rockchip-power-domain-manage-resource-conflicts-with-firmware.patch b/queue-5.10/soc-rockchip-power-domain-manage-resource-conflicts-with-firmware.patch deleted file mode 100644 index fda4b0660b..0000000000 --- a/queue-5.10/soc-rockchip-power-domain-manage-resource-conflicts-with-firmware.patch +++ /dev/null @@ -1,291 +0,0 @@ -From stable+bounces-206023-greg=kroah.com@vger.kernel.org Tue Jan 6 20:08:34 2026 -From: Sasha Levin -Date: Tue, 6 Jan 2026 13:26:52 -0500 -Subject: soc: rockchip: power-domain: Manage resource conflicts with firmware -To: stable@vger.kernel.org -Cc: Brian Norris , Peter Geis , Heiko Stuebner , Chanwoo Choi , Sasha Levin -Message-ID: <20260106182656.3115094-1-sashal@kernel.org> - -From: Brian Norris - -[ Upstream commit defec178df76e0caadd4e8ef68f3d655a2088198 ] - -On RK3399 platforms, power domains are managed mostly by the kernel -(drivers/soc/rockchip/pm_domains.c), but there are a few exceptions -where ARM Trusted Firmware has to be involved: - -(1) system suspend/resume -(2) DRAM DVFS (a.k.a., "ddrfreq") - -Exception (1) does not cause much conflict, since the kernel has -quiesced itself by the time we make the relevant PSCI call. - -Exception (2) can cause conflict, because of two actions: - -(a) ARM Trusted Firmware needs to read/modify/write the PMU_BUS_IDLE_REQ - register to idle the memory controller domain; the kernel driver - also has to touch this register for other domains. -(b) ARM Trusted Firmware needs to manage the clocks associated with - these domains. - -To elaborate on (b): idling a power domain has always required ungating -an array of clocks; see this old explanation from Rockchip: -https://lore.kernel.org/linux-arm-kernel/54503C19.9060607@rock-chips.com/ - -Historically, ARM Trusted Firmware has avoided this issue by using a -special PMU_CRU_GATEDIS_CON0 register -- this register ungates all the -necessary clocks -- when idling the memory controller. Unfortunately, -we've found that this register is not 100% sufficient; it does not turn -the relevant PLLs on [0]. - -So it's possible to trigger issues with something like the following: - -1. enable a power domain (e.g., RK3399_PD_VDU) -- kernel will - temporarily enable relevant clocks/PLLs, then turn them back off - 2. a PLL (e.g., PLL_NPLL) is part of the clock tree for - RK3399_PD_VDU's clocks but otherwise unused; NPLL is disabled -3. perform a ddrfreq transition (rk3399_dmcfreq_target() -> ... - drivers/clk/rockchip/clk-ddr.c / ROCKCHIP_SIP_DRAM_FREQ) - 4. ARM Trusted Firmware unagates VDU clocks (via PMU_CRU_GATEDIS_CON0) - 5. ARM Trusted firmware idles the memory controller domain - 6. Step 5 waits on the VDU domain/clocks, but NPLL is still off - -i.e., we hang the system. - -So for (b), we need to at a minimum manage the relevant PLLs on behalf -of firmware. It's easier to simply manage the whole clock tree, in a -similar way we do in rockchip_pd_power(). - -For (a), we need to provide mutual exclusion betwen rockchip_pd_power() -and firmware. To resolve that, we simply grab the PMU mutex and release -it when ddrfreq is done. - -The Chromium OS kernel has been carrying versions of part of this hack -for a while, based on some new custom notifiers [1]. I've rewritten as a -simple function call between the drivers, which is OK because: - - * the PMU driver isn't enabled, and we don't have this problem at all - (the firmware should have left us in an OK state, and there are no - runtime conflicts); or - * the PMU driver is present, and is a single instance. - -And the power-domain driver cannot be removed, so there's no lifetime -management to worry about. - -For completeness, there's a 'dmc_pmu_mutex' to guard (likely -theoretical?) probe()-time races. It's OK for the memory controller -driver to start running before the PMU, because the PMU will avoid any -critical actions during the block() sequence. - -[0] The RK3399 TRM for PMU_CRU_GATEDIS_CON0 only talks about ungating - clocks. Based on experimentation, we've found that it does not power - up the necessary PLLs. - -[1] CHROMIUM: soc: rockchip: power-domain: Add notifier to dmc driver - https://chromium-review.googlesource.com/q/I242dbd706d352f74ff706f5cbf42ebb92f9bcc60 - Notably, the Chromium solution only handled conflict (a), not (b). - In practice, item (b) wasn't a problem in many cases because we - never managed to fully power off PLLs. Now that the (upstream) video - decoder driver performs runtime clock management, we often power off - NPLL. - -Signed-off-by: Brian Norris -Tested-by: Peter Geis -Reviewed-by: Heiko Stuebner -Signed-off-by: Chanwoo Choi -Stable-dep-of: 73cb5f6eafb0 ("pmdomain: imx: Fix reference count leak in imx_gpc_probe()") -Signed-off-by: Sasha Levin -Signed-off-by: Greg Kroah-Hartman ---- - drivers/soc/rockchip/pm_domains.c | 118 ++++++++++++++++++++++++++++++++++++++ - include/soc/rockchip/pm_domains.h | 25 ++++++++ - 2 files changed, 143 insertions(+) - create mode 100644 include/soc/rockchip/pm_domains.h - ---- a/drivers/soc/rockchip/pm_domains.c -+++ b/drivers/soc/rockchip/pm_domains.c -@@ -8,6 +8,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -16,6 +17,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -131,6 +133,109 @@ struct rockchip_pmu { - #define DOMAIN_RK3399(pwr, status, req, wakeup) \ - DOMAIN(pwr, status, req, req, req, wakeup) - -+/* -+ * Dynamic Memory Controller may need to coordinate with us -- see -+ * rockchip_pmu_block(). -+ * -+ * dmc_pmu_mutex protects registration-time races, so DMC driver doesn't try to -+ * block() while we're initializing the PMU. -+ */ -+static DEFINE_MUTEX(dmc_pmu_mutex); -+static struct rockchip_pmu *dmc_pmu; -+ -+/* -+ * Block PMU transitions and make sure they don't interfere with ARM Trusted -+ * Firmware operations. There are two conflicts, noted in the comments below. -+ * -+ * Caller must unblock PMU transitions via rockchip_pmu_unblock(). -+ */ -+int rockchip_pmu_block(void) -+{ -+ struct rockchip_pmu *pmu; -+ struct generic_pm_domain *genpd; -+ struct rockchip_pm_domain *pd; -+ int i, ret; -+ -+ mutex_lock(&dmc_pmu_mutex); -+ -+ /* No PMU (yet)? Then we just block rockchip_pmu_probe(). */ -+ if (!dmc_pmu) -+ return 0; -+ pmu = dmc_pmu; -+ -+ /* -+ * mutex blocks all idle transitions: we can't touch the -+ * PMU_BUS_IDLE_REQ (our ".idle_offset") register while ARM Trusted -+ * Firmware might be using it. -+ */ -+ mutex_lock(&pmu->mutex); -+ -+ /* -+ * Power domain clocks: Per Rockchip, we *must* keep certain clocks -+ * enabled for the duration of power-domain transitions. Most -+ * transitions are handled by this driver, but some cases (in -+ * particular, DRAM DVFS / memory-controller idle) must be handled by -+ * firmware. Firmware can handle most clock management via a special -+ * "ungate" register (PMU_CRU_GATEDIS_CON0), but unfortunately, this -+ * doesn't handle PLLs. We can assist this transition by doing the -+ * clock management on behalf of firmware. -+ */ -+ for (i = 0; i < pmu->genpd_data.num_domains; i++) { -+ genpd = pmu->genpd_data.domains[i]; -+ if (genpd) { -+ pd = to_rockchip_pd(genpd); -+ ret = clk_bulk_enable(pd->num_clks, pd->clks); -+ if (ret < 0) { -+ dev_err(pmu->dev, -+ "failed to enable clks for domain '%s': %d\n", -+ genpd->name, ret); -+ goto err; -+ } -+ } -+ } -+ -+ return 0; -+ -+err: -+ for (i = i - 1; i >= 0; i--) { -+ genpd = pmu->genpd_data.domains[i]; -+ if (genpd) { -+ pd = to_rockchip_pd(genpd); -+ clk_bulk_disable(pd->num_clks, pd->clks); -+ } -+ } -+ mutex_unlock(&pmu->mutex); -+ mutex_unlock(&dmc_pmu_mutex); -+ -+ return ret; -+} -+EXPORT_SYMBOL_GPL(rockchip_pmu_block); -+ -+/* Unblock PMU transitions. */ -+void rockchip_pmu_unblock(void) -+{ -+ struct rockchip_pmu *pmu; -+ struct generic_pm_domain *genpd; -+ struct rockchip_pm_domain *pd; -+ int i; -+ -+ if (dmc_pmu) { -+ pmu = dmc_pmu; -+ for (i = 0; i < pmu->genpd_data.num_domains; i++) { -+ genpd = pmu->genpd_data.domains[i]; -+ if (genpd) { -+ pd = to_rockchip_pd(genpd); -+ clk_bulk_disable(pd->num_clks, pd->clks); -+ } -+ } -+ -+ mutex_unlock(&pmu->mutex); -+ } -+ -+ mutex_unlock(&dmc_pmu_mutex); -+} -+EXPORT_SYMBOL_GPL(rockchip_pmu_unblock); -+ - static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd) - { - struct rockchip_pmu *pmu = pd->pmu; -@@ -679,6 +784,12 @@ static int rockchip_pm_domain_probe(stru - - error = -ENODEV; - -+ /* -+ * Prevent any rockchip_pmu_block() from racing with the remainder of -+ * setup (clocks, register initialization). -+ */ -+ mutex_lock(&dmc_pmu_mutex); -+ - for_each_available_child_of_node(np, node) { - error = rockchip_pm_add_one_domain(pmu, node); - if (error) { -@@ -708,10 +819,17 @@ static int rockchip_pm_domain_probe(stru - goto err_out; - } - -+ /* We only expect one PMU. */ -+ if (!WARN_ON_ONCE(dmc_pmu)) -+ dmc_pmu = pmu; -+ -+ mutex_unlock(&dmc_pmu_mutex); -+ - return 0; - - err_out: - rockchip_pm_domain_cleanup(pmu); -+ mutex_unlock(&dmc_pmu_mutex); - return error; - } - ---- /dev/null -+++ b/include/soc/rockchip/pm_domains.h -@@ -0,0 +1,25 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Copyright 2022, The Chromium OS Authors. All rights reserved. -+ */ -+ -+#ifndef __SOC_ROCKCHIP_PM_DOMAINS_H__ -+#define __SOC_ROCKCHIP_PM_DOMAINS_H__ -+ -+#ifdef CONFIG_ROCKCHIP_PM_DOMAINS -+ -+int rockchip_pmu_block(void); -+void rockchip_pmu_unblock(void); -+ -+#else /* CONFIG_ROCKCHIP_PM_DOMAINS */ -+ -+static inline int rockchip_pmu_block(void) -+{ -+ return 0; -+} -+ -+static inline void rockchip_pmu_unblock(void) { } -+ -+#endif /* CONFIG_ROCKCHIP_PM_DOMAINS */ -+ -+#endif /* __SOC_ROCKCHIP_PM_DOMAINS_H__ */ diff --git a/queue-5.15/pmdomain-use-device_get_match_data.patch b/queue-5.15/pmdomain-use-device_get_match_data.patch index 8c097ab8ac..36eb29ba5e 100644 --- a/queue-5.15/pmdomain-use-device_get_match_data.patch +++ b/queue-5.15/pmdomain-use-device_get_match_data.patch @@ -94,10 +94,10 @@ Signed-off-by: Greg Kroah-Hartman void __iomem *base; --- a/drivers/soc/rockchip/pm_domains.c +++ b/drivers/soc/rockchip/pm_domains.c -@@ -9,11 +9,13 @@ +@@ -8,11 +8,13 @@ + #include #include #include - #include +#include #include #include @@ -109,7 +109,7 @@ Signed-off-by: Greg Kroah-Hartman #include #include #include -@@ -739,7 +741,6 @@ static int rockchip_pm_domain_probe(stru +@@ -634,7 +636,6 @@ static int rockchip_pm_domain_probe(stru struct device_node *node; struct device *parent; struct rockchip_pmu *pmu; @@ -117,7 +117,7 @@ Signed-off-by: Greg Kroah-Hartman const struct rockchip_pmu_info *pmu_info; int error; -@@ -748,13 +749,7 @@ static int rockchip_pm_domain_probe(stru +@@ -643,13 +644,7 @@ static int rockchip_pm_domain_probe(stru return -ENODEV; } diff --git a/queue-5.15/series b/queue-5.15/series index 3bd264c476..6e3fd164c7 100644 --- a/queue-5.15/series +++ b/queue-5.15/series @@ -471,7 +471,6 @@ mm-balloon_compaction-make-balloon-page-compaction-callbacks-static.patch mm-balloon_compaction-we-cannot-have-isolated-pages-in-the-balloon-list.patch mm-balloon_compaction-convert-balloon_page_delete-to-balloon_page_finalize.patch powerpc-pseries-cmm-adjust-balloon_migrate-when-migrating-pages.patch -soc-rockchip-power-domain-manage-resource-conflicts-with-firmware.patch pmdomain-use-device_get_match_data.patch pmdomain-imx-fix-reference-count-leak-in-imx_gpc_probe.patch lockd-fix-vfs_test_lock-calls.patch @@ -495,3 +494,6 @@ selftests-net-test_vxlan_under_vrf-fix-hv-connectivity-test.patch x86-remove-__range_not_ok.patch mm-fix-copy_from_user_nofault.patch pwm-stm32-always-program-polarity.patch +ext4-filesystems-without-casefold-feature-cannot-be-mounted-with-siphash.patch +ext4-factor-out-ext4_hash_info_init.patch +ext4-fix-error-message-when-rejecting-the-default-hash.patch diff --git a/queue-5.15/soc-rockchip-power-domain-manage-resource-conflicts-with-firmware.patch b/queue-5.15/soc-rockchip-power-domain-manage-resource-conflicts-with-firmware.patch deleted file mode 100644 index bfdfdcebcd..0000000000 --- a/queue-5.15/soc-rockchip-power-domain-manage-resource-conflicts-with-firmware.patch +++ /dev/null @@ -1,291 +0,0 @@ -From stable+bounces-206019-greg=kroah.com@vger.kernel.org Tue Jan 6 19:57:04 2026 -From: Sasha Levin -Date: Tue, 6 Jan 2026 13:10:14 -0500 -Subject: soc: rockchip: power-domain: Manage resource conflicts with firmware -To: stable@vger.kernel.org -Cc: Brian Norris , Peter Geis , Heiko Stuebner , Chanwoo Choi , Sasha Levin -Message-ID: <20260106181021.3109327-1-sashal@kernel.org> - -From: Brian Norris - -[ Upstream commit defec178df76e0caadd4e8ef68f3d655a2088198 ] - -On RK3399 platforms, power domains are managed mostly by the kernel -(drivers/soc/rockchip/pm_domains.c), but there are a few exceptions -where ARM Trusted Firmware has to be involved: - -(1) system suspend/resume -(2) DRAM DVFS (a.k.a., "ddrfreq") - -Exception (1) does not cause much conflict, since the kernel has -quiesced itself by the time we make the relevant PSCI call. - -Exception (2) can cause conflict, because of two actions: - -(a) ARM Trusted Firmware needs to read/modify/write the PMU_BUS_IDLE_REQ - register to idle the memory controller domain; the kernel driver - also has to touch this register for other domains. -(b) ARM Trusted Firmware needs to manage the clocks associated with - these domains. - -To elaborate on (b): idling a power domain has always required ungating -an array of clocks; see this old explanation from Rockchip: -https://lore.kernel.org/linux-arm-kernel/54503C19.9060607@rock-chips.com/ - -Historically, ARM Trusted Firmware has avoided this issue by using a -special PMU_CRU_GATEDIS_CON0 register -- this register ungates all the -necessary clocks -- when idling the memory controller. Unfortunately, -we've found that this register is not 100% sufficient; it does not turn -the relevant PLLs on [0]. - -So it's possible to trigger issues with something like the following: - -1. enable a power domain (e.g., RK3399_PD_VDU) -- kernel will - temporarily enable relevant clocks/PLLs, then turn them back off - 2. a PLL (e.g., PLL_NPLL) is part of the clock tree for - RK3399_PD_VDU's clocks but otherwise unused; NPLL is disabled -3. perform a ddrfreq transition (rk3399_dmcfreq_target() -> ... - drivers/clk/rockchip/clk-ddr.c / ROCKCHIP_SIP_DRAM_FREQ) - 4. ARM Trusted Firmware unagates VDU clocks (via PMU_CRU_GATEDIS_CON0) - 5. ARM Trusted firmware idles the memory controller domain - 6. Step 5 waits on the VDU domain/clocks, but NPLL is still off - -i.e., we hang the system. - -So for (b), we need to at a minimum manage the relevant PLLs on behalf -of firmware. It's easier to simply manage the whole clock tree, in a -similar way we do in rockchip_pd_power(). - -For (a), we need to provide mutual exclusion betwen rockchip_pd_power() -and firmware. To resolve that, we simply grab the PMU mutex and release -it when ddrfreq is done. - -The Chromium OS kernel has been carrying versions of part of this hack -for a while, based on some new custom notifiers [1]. I've rewritten as a -simple function call between the drivers, which is OK because: - - * the PMU driver isn't enabled, and we don't have this problem at all - (the firmware should have left us in an OK state, and there are no - runtime conflicts); or - * the PMU driver is present, and is a single instance. - -And the power-domain driver cannot be removed, so there's no lifetime -management to worry about. - -For completeness, there's a 'dmc_pmu_mutex' to guard (likely -theoretical?) probe()-time races. It's OK for the memory controller -driver to start running before the PMU, because the PMU will avoid any -critical actions during the block() sequence. - -[0] The RK3399 TRM for PMU_CRU_GATEDIS_CON0 only talks about ungating - clocks. Based on experimentation, we've found that it does not power - up the necessary PLLs. - -[1] CHROMIUM: soc: rockchip: power-domain: Add notifier to dmc driver - https://chromium-review.googlesource.com/q/I242dbd706d352f74ff706f5cbf42ebb92f9bcc60 - Notably, the Chromium solution only handled conflict (a), not (b). - In practice, item (b) wasn't a problem in many cases because we - never managed to fully power off PLLs. Now that the (upstream) video - decoder driver performs runtime clock management, we often power off - NPLL. - -Signed-off-by: Brian Norris -Tested-by: Peter Geis -Reviewed-by: Heiko Stuebner -Signed-off-by: Chanwoo Choi -Stable-dep-of: 73cb5f6eafb0 ("pmdomain: imx: Fix reference count leak in imx_gpc_probe()") -Signed-off-by: Sasha Levin -Signed-off-by: Greg Kroah-Hartman ---- - drivers/soc/rockchip/pm_domains.c | 118 ++++++++++++++++++++++++++++++++++++++ - include/soc/rockchip/pm_domains.h | 25 ++++++++ - 2 files changed, 143 insertions(+) - create mode 100644 include/soc/rockchip/pm_domains.h - ---- a/drivers/soc/rockchip/pm_domains.c -+++ b/drivers/soc/rockchip/pm_domains.c -@@ -8,6 +8,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -16,6 +17,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -139,6 +141,109 @@ struct rockchip_pmu { - #define DOMAIN_RK3568(name, pwr, req, wakeup) \ - DOMAIN_M(name, pwr, pwr, req, req, req, wakeup) - -+/* -+ * Dynamic Memory Controller may need to coordinate with us -- see -+ * rockchip_pmu_block(). -+ * -+ * dmc_pmu_mutex protects registration-time races, so DMC driver doesn't try to -+ * block() while we're initializing the PMU. -+ */ -+static DEFINE_MUTEX(dmc_pmu_mutex); -+static struct rockchip_pmu *dmc_pmu; -+ -+/* -+ * Block PMU transitions and make sure they don't interfere with ARM Trusted -+ * Firmware operations. There are two conflicts, noted in the comments below. -+ * -+ * Caller must unblock PMU transitions via rockchip_pmu_unblock(). -+ */ -+int rockchip_pmu_block(void) -+{ -+ struct rockchip_pmu *pmu; -+ struct generic_pm_domain *genpd; -+ struct rockchip_pm_domain *pd; -+ int i, ret; -+ -+ mutex_lock(&dmc_pmu_mutex); -+ -+ /* No PMU (yet)? Then we just block rockchip_pmu_probe(). */ -+ if (!dmc_pmu) -+ return 0; -+ pmu = dmc_pmu; -+ -+ /* -+ * mutex blocks all idle transitions: we can't touch the -+ * PMU_BUS_IDLE_REQ (our ".idle_offset") register while ARM Trusted -+ * Firmware might be using it. -+ */ -+ mutex_lock(&pmu->mutex); -+ -+ /* -+ * Power domain clocks: Per Rockchip, we *must* keep certain clocks -+ * enabled for the duration of power-domain transitions. Most -+ * transitions are handled by this driver, but some cases (in -+ * particular, DRAM DVFS / memory-controller idle) must be handled by -+ * firmware. Firmware can handle most clock management via a special -+ * "ungate" register (PMU_CRU_GATEDIS_CON0), but unfortunately, this -+ * doesn't handle PLLs. We can assist this transition by doing the -+ * clock management on behalf of firmware. -+ */ -+ for (i = 0; i < pmu->genpd_data.num_domains; i++) { -+ genpd = pmu->genpd_data.domains[i]; -+ if (genpd) { -+ pd = to_rockchip_pd(genpd); -+ ret = clk_bulk_enable(pd->num_clks, pd->clks); -+ if (ret < 0) { -+ dev_err(pmu->dev, -+ "failed to enable clks for domain '%s': %d\n", -+ genpd->name, ret); -+ goto err; -+ } -+ } -+ } -+ -+ return 0; -+ -+err: -+ for (i = i - 1; i >= 0; i--) { -+ genpd = pmu->genpd_data.domains[i]; -+ if (genpd) { -+ pd = to_rockchip_pd(genpd); -+ clk_bulk_disable(pd->num_clks, pd->clks); -+ } -+ } -+ mutex_unlock(&pmu->mutex); -+ mutex_unlock(&dmc_pmu_mutex); -+ -+ return ret; -+} -+EXPORT_SYMBOL_GPL(rockchip_pmu_block); -+ -+/* Unblock PMU transitions. */ -+void rockchip_pmu_unblock(void) -+{ -+ struct rockchip_pmu *pmu; -+ struct generic_pm_domain *genpd; -+ struct rockchip_pm_domain *pd; -+ int i; -+ -+ if (dmc_pmu) { -+ pmu = dmc_pmu; -+ for (i = 0; i < pmu->genpd_data.num_domains; i++) { -+ genpd = pmu->genpd_data.domains[i]; -+ if (genpd) { -+ pd = to_rockchip_pd(genpd); -+ clk_bulk_disable(pd->num_clks, pd->clks); -+ } -+ } -+ -+ mutex_unlock(&pmu->mutex); -+ } -+ -+ mutex_unlock(&dmc_pmu_mutex); -+} -+EXPORT_SYMBOL_GPL(rockchip_pmu_unblock); -+ - static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd) - { - struct rockchip_pmu *pmu = pd->pmu; -@@ -690,6 +795,12 @@ static int rockchip_pm_domain_probe(stru - - error = -ENODEV; - -+ /* -+ * Prevent any rockchip_pmu_block() from racing with the remainder of -+ * setup (clocks, register initialization). -+ */ -+ mutex_lock(&dmc_pmu_mutex); -+ - for_each_available_child_of_node(np, node) { - error = rockchip_pm_add_one_domain(pmu, node); - if (error) { -@@ -719,10 +830,17 @@ static int rockchip_pm_domain_probe(stru - goto err_out; - } - -+ /* We only expect one PMU. */ -+ if (!WARN_ON_ONCE(dmc_pmu)) -+ dmc_pmu = pmu; -+ -+ mutex_unlock(&dmc_pmu_mutex); -+ - return 0; - - err_out: - rockchip_pm_domain_cleanup(pmu); -+ mutex_unlock(&dmc_pmu_mutex); - return error; - } - ---- /dev/null -+++ b/include/soc/rockchip/pm_domains.h -@@ -0,0 +1,25 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Copyright 2022, The Chromium OS Authors. All rights reserved. -+ */ -+ -+#ifndef __SOC_ROCKCHIP_PM_DOMAINS_H__ -+#define __SOC_ROCKCHIP_PM_DOMAINS_H__ -+ -+#ifdef CONFIG_ROCKCHIP_PM_DOMAINS -+ -+int rockchip_pmu_block(void); -+void rockchip_pmu_unblock(void); -+ -+#else /* CONFIG_ROCKCHIP_PM_DOMAINS */ -+ -+static inline int rockchip_pmu_block(void) -+{ -+ return 0; -+} -+ -+static inline void rockchip_pmu_unblock(void) { } -+ -+#endif /* CONFIG_ROCKCHIP_PM_DOMAINS */ -+ -+#endif /* __SOC_ROCKCHIP_PM_DOMAINS_H__ */