From: Alex Coplan <alex.coplan@arm.com>
Date: Wed, 4 Oct 2023 13:13:00 +0000 (+0100)
Subject: aarch64, testsuite: Tweak sve/pcs/args_9.c to allow stps
X-Git-Tag: basepoints/gcc-15~5398
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=cf776eebe86b8b75697de55a6a8ade72ce9f66c5;p=thirdparty%2Fgcc.git

aarch64, testsuite: Tweak sve/pcs/args_9.c to allow stps

With the new ldp/stp pass enabled, there is a change in the codegen for
this test as follows:

        add     x8, sp, 16
        ptrue   p3.h, mul3
        str     p3, [x8]
-       str     x8, [sp, 8]
-       str     x9, [sp]
+       stp     x9, x8, [sp]
        ptrue   p3.d, vl8
        ptrue   p2.s, vl7
        ptrue   p1.h, vl6

i.e. we now form an stp that we were missing previously. This patch
adjusts the scan-assembler such that it should pass whether or not
we form the stp.

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/sve/pcs/args_9.c: Adjust scan-assemblers to
	allow for stp.
---

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_9.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_9.c
index ad9affadf02a..942a44ab4483 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_9.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_9.c
@@ -45,5 +45,5 @@ caller (int64_t *x0, int16_t *x1, svbool_t p0)
   return svcntp_b8 (res, res);
 }
 
-/* { dg-final { scan-assembler {\tptrue\t(p[0-9]+)\.b, mul3\n\tstr\t\1, \[(x[0-9]+)\]\n.*\tstr\t\2, \[sp\]\n} } } */
-/* { dg-final { scan-assembler {\tptrue\t(p[0-9]+)\.h, mul3\n\tstr\t\1, \[(x[0-9]+)\]\n.*\tstr\t\2, \[sp, 8\]\n} } } */
+/* { dg-final { scan-assembler {\tptrue\t(p[0-9]+)\.b, mul3\n\tstr\t\1, \[(x[0-9]+)\]\n.*\t(?:str\t\2, \[sp\]|stp\t\2, x[0-9]+, \[sp\])\n} } } */
+/* { dg-final { scan-assembler {\tptrue\t(p[0-9]+)\.h, mul3\n\tstr\t\1, \[(x[0-9]+)\]\n.*\t(?:str\t\2, \[sp, 8\]|stp\tx[0-9]+, \2, \[sp\])\n} } } */