From: Lehua Ding <lehua.ding@rivai.ai>
Date: Wed, 20 Sep 2023 05:35:16 +0000 (+0800)
Subject: RISC-V: Fixed ICE caused by missing operand
X-Git-Tag: basepoints/gcc-15~5973
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=d024a31a09d18d2586769602205a60ff3afe568c;p=thirdparty%2Fgcc.git

RISC-V: Fixed ICE caused by missing operand

This ICE appears in GCC compiled with -O2 flags.

	PR target/111488

gcc/ChangeLog:

	* config/riscv/autovec-opt.md: Add missed operand.
---

diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index cef9f157e996..66c77ad6ebb3 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -957,7 +957,8 @@
     riscv_vector::emit_vlmax_insn (extend_icode, riscv_vector::UNARY_OP,
                                    extend_ops);
 
-    rtx ops[] = {operands[0], tmp, operands[3], operands[1]};
+    rtx ops[] = {operands[0], tmp, operands[3], operands[1],
+                 RVV_VUNDEF(<MODE>mode)};
     riscv_vector::emit_vlmax_insn (code_for_pred_mul_plus (<MODE>mode),
 				   riscv_vector::TERNARY_OP, ops);
     DONE;
@@ -1008,7 +1009,8 @@
     rtx ext_ops[] = {tmp, operands[2]};
     riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, ext_ops);
 
-    rtx ops[] = {operands[0], tmp, operands[3], operands[1]};
+    rtx ops[] = {operands[0], tmp, operands[3], operands[1],
+                 RVV_VUNDEF(<MODE>mode)};
     riscv_vector::emit_vlmax_insn (code_for_pred_mul (PLUS, <MODE>mode),
 				   riscv_vector::TERNARY_OP_FRM_DYN, ops);
     DONE;
@@ -1059,7 +1061,8 @@
     rtx ext_ops[] = {tmp, operands[2]};
     riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, ext_ops);
 
-    rtx ops[] = {operands[0], tmp, operands[3], operands[1]};
+    rtx ops[] = {operands[0], tmp, operands[3], operands[1],
+                 RVV_VUNDEF(<MODE>mode)};
     riscv_vector::emit_vlmax_insn (code_for_pred_mul_neg (PLUS, <MODE>mode),
 				   riscv_vector::TERNARY_OP_FRM_DYN, ops);
     DONE;
@@ -1110,7 +1113,8 @@
     rtx ext_ops[] = {tmp, operands[2]};
     riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, ext_ops);
 
-    rtx ops[] = {operands[0], tmp, operands[3], operands[1]};
+    rtx ops[] = {operands[0], tmp, operands[3], operands[1],
+                 RVV_VUNDEF(<MODE>mode)};
     riscv_vector::emit_vlmax_insn (code_for_pred_mul (MINUS, <MODE>mode),
 				   riscv_vector::TERNARY_OP_FRM_DYN, ops);
     DONE;
@@ -1163,7 +1167,8 @@
     rtx ext_ops[] = {tmp, operands[2]};
     riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, ext_ops);
 
-    rtx ops[] = {operands[0], tmp, operands[3], operands[1]};
+    rtx ops[] = {operands[0], tmp, operands[3], operands[1],
+                 RVV_VUNDEF(<MODE>mode)};
     riscv_vector::emit_vlmax_insn (code_for_pred_mul_neg (MINUS, <MODE>mode),
 				   riscv_vector::TERNARY_OP_FRM_DYN, ops);
     DONE;