From: Richard Henderson <rth@redhat.com>
Date: Tue, 20 Sep 2005 06:11:42 +0000 (+0000)
Subject:         [BZ #1358]
X-Git-Tag: cvs/fedora-glibc-2_3-20051017T0518~41
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=d0687a414dbfa634d7057b5f5c11ebcef09b6b95;p=thirdparty%2Fglibc.git

    [BZ #1358]
        * sysdeps/unix/alpha/sysdep.h (inline_syscall1): Copy argument(s)
        to a temporary first.
        (inline_syscall2, inline_syscall3, inline_syscall4): Likewise.
        (inline_syscall5, inline_syscall6): Likewise.

        * sysdeps/alpha/ldiv.S (lldiv): Add alias.
---

diff --git a/ChangeLog b/ChangeLog
index 8567b5f3f62..a05ebe5417d 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,13 @@
+2005-09-19  Richard Henderson  <rth@redhat.com>
+
+        [BZ #1358]
+        * sysdeps/unix/alpha/sysdep.h (inline_syscall1): Copy argument(s)
+        to a temporary first.
+        (inline_syscall2, inline_syscall3, inline_syscall4): Likewise.
+        (inline_syscall5, inline_syscall6): Likewise.
+
+        * sysdeps/alpha/ldiv.S (lldiv): Add alias.
+
 2005-07-28  Thomas Schwinge  <schwinge@nic-nac-project.de>
 
 	[BZ #1137]
diff --git a/sysdeps/alpha/ldiv.S b/sysdeps/alpha/ldiv.S
index 39096727824..0a971a7ed00 100644
--- a/sysdeps/alpha/ldiv.S
+++ b/sysdeps/alpha/ldiv.S
@@ -214,3 +214,5 @@ $divbyzero:
 	ret
 
 	.end	ldiv
+
+weak_alias (ldiv, lldiv)
diff --git a/sysdeps/unix/alpha/sysdep.h b/sysdeps/unix/alpha/sysdep.h
index f9f1dd6e41b..a154db8e411 100644
--- a/sysdeps/unix/alpha/sysdep.h
+++ b/sysdeps/unix/alpha/sysdep.h
@@ -242,9 +242,10 @@ __LABEL(name)						\
 	register long _sc_0 inline_syscall_r0_asm;		\
 	register long _sc_16 __asm__("$16");			\
 	register long _sc_19 __asm__("$19");			\
+	register long _tmp_16 = (long) (arg1);			\
 								\
 	_sc_0 = name;						\
-	_sc_16 = (long) (arg1);					\
+	_sc_16 = _tmp_16;					\
 	__asm__ __volatile__					\
 	  ("callsys # %0 %1 <= %2 %3"				\
 	   : inline_syscall_r0_out_constraint (_sc_0),		\
@@ -261,10 +262,12 @@ __LABEL(name)						\
 	register long _sc_16 __asm__("$16");			\
 	register long _sc_17 __asm__("$17");			\
 	register long _sc_19 __asm__("$19");			\
+	register long _tmp_16 = (long) (arg1);			\
+	register long _tmp_17 = (long) (arg2);			\
 								\
 	_sc_0 = name;						\
-	_sc_16 = (long) (arg1);					\
-	_sc_17 = (long) (arg2);					\
+	_sc_16 = _tmp_16;					\
+	_sc_17 = _tmp_17;					\
 	__asm__ __volatile__					\
 	  ("callsys # %0 %1 <= %2 %3 %4"			\
 	   : inline_syscall_r0_out_constraint (_sc_0),		\
@@ -282,11 +285,14 @@ __LABEL(name)						\
 	register long _sc_17 __asm__("$17");			\
 	register long _sc_18 __asm__("$18");			\
 	register long _sc_19 __asm__("$19");			\
+	register long _tmp_16 = (long) (arg1);			\
+	register long _tmp_17 = (long) (arg2);			\
+	register long _tmp_18 = (long) (arg3);			\
 								\
 	_sc_0 = name;						\
-	_sc_16 = (long) (arg1);					\
-	_sc_17 = (long) (arg2);					\
-	_sc_18 = (long) (arg3);					\
+	_sc_16 = _tmp_16;					\
+	_sc_17 = _tmp_17;					\
+	_sc_18 = _tmp_18;					\
 	__asm__ __volatile__					\
 	  ("callsys # %0 %1 <= %2 %3 %4 %5"			\
 	   : inline_syscall_r0_out_constraint (_sc_0),		\
@@ -305,12 +311,16 @@ __LABEL(name)						\
 	register long _sc_17 __asm__("$17");			\
 	register long _sc_18 __asm__("$18");			\
 	register long _sc_19 __asm__("$19");			\
+	register long _tmp_16 = (long) (arg1);			\
+	register long _tmp_17 = (long) (arg2);			\
+	register long _tmp_18 = (long) (arg3);			\
+	register long _tmp_19 = (long) (arg4);			\
 								\
 	_sc_0 = name;						\
-	_sc_16 = (long) (arg1);					\
-	_sc_17 = (long) (arg2);					\
-	_sc_18 = (long) (arg3);					\
-	_sc_19 = (long) (arg4);					\
+	_sc_16 = _tmp_16;					\
+	_sc_17 = _tmp_17;					\
+	_sc_18 = _tmp_18;					\
+	_sc_19 = _tmp_19;					\
 	__asm__ __volatile__					\
 	  ("callsys # %0 %1 <= %2 %3 %4 %5 %6"			\
 	   : inline_syscall_r0_out_constraint (_sc_0),		\
@@ -330,13 +340,18 @@ __LABEL(name)						\
 	register long _sc_18 __asm__("$18");			\
 	register long _sc_19 __asm__("$19");			\
 	register long _sc_20 __asm__("$20");			\
+	register long _tmp_16 = (long) (arg1);			\
+	register long _tmp_17 = (long) (arg2);			\
+	register long _tmp_18 = (long) (arg3);			\
+	register long _tmp_19 = (long) (arg4);			\
+	register long _tmp_20 = (long) (arg5);			\
 								\
 	_sc_0 = name;						\
-	_sc_16 = (long) (arg1);					\
-	_sc_17 = (long) (arg2);					\
-	_sc_18 = (long) (arg3);					\
-	_sc_19 = (long) (arg4);					\
-	_sc_20 = (long) (arg5);					\
+	_sc_16 = _tmp_16;					\
+	_sc_17 = _tmp_17;					\
+	_sc_18 = _tmp_18;					\
+	_sc_19 = _tmp_19;					\
+	_sc_20 = _tmp_20;					\
 	__asm__ __volatile__					\
 	  ("callsys # %0 %1 <= %2 %3 %4 %5 %6 %7"		\
 	   : inline_syscall_r0_out_constraint (_sc_0),		\
@@ -357,14 +372,20 @@ __LABEL(name)						\
 	register long _sc_19 __asm__("$19");			\
 	register long _sc_20 __asm__("$20");			\
 	register long _sc_21 __asm__("$21");			\
+	register long _tmp_16 = (long) (arg1);			\
+	register long _tmp_17 = (long) (arg2);			\
+	register long _tmp_18 = (long) (arg3);			\
+	register long _tmp_19 = (long) (arg4);			\
+	register long _tmp_20 = (long) (arg5);			\
+	register long _tmp_21 = (long) (arg6);			\
 								\
 	_sc_0 = name;						\
-	_sc_16 = (long) (arg1);					\
-	_sc_17 = (long) (arg2);					\
-	_sc_18 = (long) (arg3);					\
-	_sc_19 = (long) (arg4);					\
-	_sc_20 = (long) (arg5);					\
-	_sc_21 = (long) (arg6);					\
+	_sc_16 = _tmp_16;					\
+	_sc_17 = _tmp_17;					\
+	_sc_18 = _tmp_18;					\
+	_sc_19 = _tmp_19;					\
+	_sc_20 = _tmp_20;					\
+	_sc_21 = _tmp_21;					\
 	__asm__ __volatile__					\
 	  ("callsys # %0 %1 <= %2 %3 %4 %5 %6 %7 %8"		\
 	   : inline_syscall_r0_out_constraint (_sc_0),		\