From: Richard Henderson Date: Thu, 4 Jun 2026 23:48:33 +0000 (-0700) Subject: target/arm: Implement SVE bitwise unary operations (predicated, zeroing) X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=d0ea7d02591b2f199eda006cbf88fd17a18566ea;p=thirdparty%2Fqemu.git target/arm: Implement SVE bitwise unary operations (predicated, zeroing) This includes CLS, CLZ, CNT, CNOT, NOT, FABS, FNEG. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20260604234852.573178-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- diff --git a/target/arm/tcg/sve.decode b/target/arm/tcg/sve.decode index 31b65fab1b..e79b5e84c1 100644 --- a/target/arm/tcg/sve.decode +++ b/target/arm/tcg/sve.decode @@ -400,6 +400,14 @@ NOT_zpz_m 00000100 .. 011 110 101 ... ..... ..... @rd_pg_rn FABS_m 00000100 .. 011 100 101 ... ..... ..... @rd_pg_rn FNEG_m 00000100 .. 011 101 101 ... ..... ..... @rd_pg_rn +CLS_z 00000100 .. 001 000 101 ... ..... ..... @rd_pg_rn +CLZ_z 00000100 .. 001 001 101 ... ..... ..... @rd_pg_rn +CNT_zpz_z 00000100 .. 001 010 101 ... ..... ..... @rd_pg_rn +CNOT_z 00000100 .. 001 011 101 ... ..... ..... @rd_pg_rn +NOT_zpz_z 00000100 .. 001 110 101 ... ..... ..... @rd_pg_rn +FABS_z 00000100 .. 001 100 101 ... ..... ..... @rd_pg_rn +FNEG_z 00000100 .. 001 101 101 ... ..... ..... @rd_pg_rn + # SVE integer unary operations (predicated) # Note esz > original size for extensions. ABS_m 00000100 .. 010 110 101 ... ..... ..... @rd_pg_rn diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index afbed77ec3..d6a1683719 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -781,30 +781,41 @@ static gen_helper_gvec_3 * const sve_cls_fns[4] = { gen_helper_sve_cls_s, gen_helper_sve_cls_d, }; TRANS_FEAT(CLS_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, sve_cls_fns[a->esz], a, 0) +TRANS_FEAT(CLS_z, aa64_sme2p2_or_sve2p2, gen_gvec_ool_arg_zpz, sve_cls_fns[a->esz], a, 1) static gen_helper_gvec_3 * const sve_clz_fns[4] = { gen_helper_sve_clz_b, gen_helper_sve_clz_h, gen_helper_sve_clz_s, gen_helper_sve_clz_d, }; TRANS_FEAT(CLZ_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, sve_clz_fns[a->esz], a, 0) +TRANS_FEAT(CLZ_z, aa64_sme2p2_or_sve2p2, gen_gvec_ool_arg_zpz, sve_clz_fns[a->esz], a, 1) static gen_helper_gvec_3 * const sve_cnt_zpz_fns[4] = { gen_helper_sve_cnt_zpz_b, gen_helper_sve_cnt_zpz_h, gen_helper_sve_cnt_zpz_s, gen_helper_sve_cnt_zpz_d, }; -TRANS_FEAT(CNT_zpz_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, sve_cnt_zpz_fns[a->esz], a, 0) +TRANS_FEAT(CNT_zpz_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, + sve_cnt_zpz_fns[a->esz], a, 0) +TRANS_FEAT(CNT_zpz_z, aa64_sme2p2_or_sve2p2, gen_gvec_ool_arg_zpz, + sve_cnt_zpz_fns[a->esz], a, 1) static gen_helper_gvec_3 * const sve_cnot_fns[4] = { gen_helper_sve_cnot_b, gen_helper_sve_cnot_h, gen_helper_sve_cnot_s, gen_helper_sve_cnot_d, }; -TRANS_FEAT(CNOT_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, sve_cnot_fns[a->esz], a, 0) +TRANS_FEAT(CNOT_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, + sve_cnot_fns[a->esz], a, 0) +TRANS_FEAT(CNOT_z, aa64_sme2p2_or_sve2p2, gen_gvec_ool_arg_zpz, + sve_cnot_fns[a->esz], a, 1) static gen_helper_gvec_3 * const sve_not_zpz_fns[4] = { gen_helper_sve_not_zpz_b, gen_helper_sve_not_zpz_h, gen_helper_sve_not_zpz_s, gen_helper_sve_not_zpz_d, }; -TRANS_FEAT(NOT_zpz_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, sve_not_zpz_fns[a->esz], a, 0) +TRANS_FEAT(NOT_zpz_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, + sve_not_zpz_fns[a->esz], a, 0) +TRANS_FEAT(NOT_zpz_z, aa64_sme2p2_or_sve2p2, gen_gvec_ool_arg_zpz, + sve_not_zpz_fns[a->esz], a, 1) static gen_helper_gvec_3 * const sve_abs_fns[4] = { gen_helper_sve_abs_b, gen_helper_sve_abs_h, @@ -857,6 +868,8 @@ static gen_helper_gvec_3 * const fabs_ah_fns[4] = { }; TRANS_FEAT(FABS_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, s->fpcr_ah ? fabs_ah_fns[a->esz] : fabs_fns[a->esz], a, 0) +TRANS_FEAT(FABS_z, aa64_sme2p2_or_sve2p2, gen_gvec_ool_arg_zpz, + s->fpcr_ah ? fabs_ah_fns[a->esz] : fabs_fns[a->esz], a, 1) static gen_helper_gvec_3 * const fneg_fns[4] = { NULL, gen_helper_sve_fneg_h, @@ -868,6 +881,8 @@ static gen_helper_gvec_3 * const fneg_ah_fns[4] = { }; TRANS_FEAT(FNEG_m, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, s->fpcr_ah ? fneg_ah_fns[a->esz] : fneg_fns[a->esz], a, 0) +TRANS_FEAT(FNEG_z, aa64_sme2p2_or_sve2p2, gen_gvec_ool_arg_zpz, + s->fpcr_ah ? fneg_ah_fns[a->esz] : fneg_fns[a->esz], a, 1) static gen_helper_gvec_3 * const sxtb_fns[4] = { NULL, gen_helper_sve_sxtb_h,