From: Horatiu Vultur Date: Wed, 19 Nov 2025 13:47:50 +0000 (+0100) Subject: ARM: dts: microchip: lan966x: Fix the access to the PHYs for pcb8290 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=d1a6f1259b0bb415107e83f6403a2ecb945d042f;p=thirdparty%2Fkernel%2Flinux.git ARM: dts: microchip: lan966x: Fix the access to the PHYs for pcb8290 The problem is that the MDIO controller can't detect any of the PHYs. The reason is that the lan966x is not pulling high the GPIO 53 that is connected to the PHYs reset GPIO. Without doing this the PHYs are kept in reset. The mdio controller framework has the possibility to control a GPIO to release the reset of the PHYs. So take advantage of this and set line to be high before accessing the PHYs. Signed-off-by: Horatiu Vultur Reviewed-by: Claudiu Beznea Reviewed-by: Andrew Lunn Link: https://lore.kernel.org/r/20251119134750.394655-1-horatiu.vultur@microchip.com [claudiu.beznea: add microchip in patch title, s/possiblity/possibility in patch description] Signed-off-by: Claudiu Beznea --- diff --git a/arch/arm/boot/dts/microchip/lan966x-pcb8290.dts b/arch/arm/boot/dts/microchip/lan966x-pcb8290.dts index 3b7577e48b467..50bd29572f3ed 100644 --- a/arch/arm/boot/dts/microchip/lan966x-pcb8290.dts +++ b/arch/arm/boot/dts/microchip/lan966x-pcb8290.dts @@ -54,6 +54,7 @@ &mdio0 { pinctrl-0 = <&miim_a_pins>; pinctrl-names = "default"; + reset-gpios = <&gpio 53 GPIO_ACTIVE_LOW>; status = "okay"; ext_phy0: ethernet-phy@7 {