From: Ankit Nautiyal Date: Wed, 30 Oct 2024 04:10:35 +0000 (+0530) Subject: drm/i915/dp: Ensure hactive is divisible by slice count X-Git-Tag: v6.14-rc1~174^2~12^2~168 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=d1f34623ad18524af3c54f92c3baaa4af1d7b3fd;p=thirdparty%2Fkernel%2Fstable.git drm/i915/dp: Ensure hactive is divisible by slice count According to the DSC spec, the slice width should be chosen such that the picture width (hactive) is evenly divisible by the slice width. If not, extra pixels (padding) must be added to the last slice to ensure all slices have the same width. Currently, we do not support handling these extra pixels. Therefore, select a slice count that evenly divides the hactive (slice_width = hactive / slice_count). This check is already implemented for DSI, where the slice count is selected from the BIOS. For DP, currently with 1, 2, 4 slices per pipe it is unlikely to have slice count not being able to divide hactive, but with 3 DSC engines and 3 slices, we can have such cases. Adding this check prepares for future scenarios where such configurations might be used. Signed-off-by: Ankit Nautiyal Reviewed-by: Suraj Kandpal Link: https://patchwork.freedesktop.org/patch/msgid/20241030041036.1238006-7-ankit.k.nautiyal@intel.com --- diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 5b120d3ad23dd..303852d469e8f 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1038,6 +1038,9 @@ u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector, if (num_joined_pipes > 1 && valid_dsc_slicecount[i] < 2) continue; + if (mode_hdisplay % test_slice_count) + continue; + if (min_slice_count <= test_slice_count) return test_slice_count; }