From: Joern Rennecke Date: Wed, 27 Sep 2023 09:05:13 +0000 (+0100) Subject: Harden scan patterns with a bit of scripting: X-Git-Tag: basepoints/gcc-15~5845 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=d326bb6d7588425d013791299272f913fb23e56d;p=thirdparty%2Fgcc.git Harden scan patterns with a bit of scripting: $ egrep -r 'scan-assembler(|-not|-times) "[[:alnum:].]{1,7}"' riscv $ egrep -rl 'scan-assembler(|-not|-times) "[[:alnum:].]{1,7}"' riscv > files $ cat edcmds g/\(scan-assembler\(\|-not\|-times\) \+\)"\([[:alnum:]]\{1,5\}\)\.\([[:alpha:].]\{1,3\}\)"/s//\1{\\m\3\\.\4\\M}/ g/\(scan-assembler\(\|-not\|-times\) \+\)"\([[:alnum:]]\{1,7\}\)"/s//\1{\\m\3}/ w q $ sed 's/.*/ed & < edcmds/' < files > tmp $ source tmp gcc/testsuite/ * gcc.target/riscv/shift-shift-1.c: Avoid spurious pattern matches. * gcc.target/riscv/shift-shift-3.c: Likewise. * gcc.target/riscv/zba-shNadd-01.c: Likewise. * gcc.target/riscv/zba-shNadd-02.c: Likewise. * gcc.target/riscv/zbb-andn-orn-xnor-01.c: Likewise. * gcc.target/riscv/zbb-andn-orn-xnor-02.c: Likewise. * gcc.target/riscv/zbb-min-max.c: Likewise. * gcc.target/riscv/zero-extend-1.c: Likewise. * gcc.target/riscv/zero-extend-2.c: Likewise. * gcc.target/riscv/zero-extend-3.c: Likewise. * gcc.target/riscv/zero-extend-4.c: Likewise. * gcc.target/riscv/zero-extend-5.c: Likewise. * gcc.target/riscv/_Float16-soft-2.c: Likewise. * gcc.target/riscv/_Float16-soft-3.c: Likewise. * gcc.target/riscv/_Float16-zfh-1.c: Likewise. * gcc.target/riscv/_Float16-zfh-2.c: Likewise. * gcc.target/riscv/_Float16-zfh-3.c: Likewise. * gcc.target/riscv/and-extend-1.c: Likewise. * gcc.target/riscv/and-extend-2.c: Likewise. * gcc.target/riscv/pr108987.c: Likewise. * gcc.target/riscv/ret-1.c: Likewise. * gcc.target/riscv/rvv/autovec/align-1.c: Likewise. * gcc.target/riscv/rvv/autovec/align-2.c: Likewise. * gcc.target/riscv/zba-shNadd-04.c: Likewise. * gcc.target/riscv/zba-shNadd-07.c: Likewise. * gcc.target/riscv/zbb-rol-ror-02.c: Likewise. * gcc.target/riscv/zbbw.c: Likewise. * gcc.target/riscv/zbc32.c: Likewise. * gcc.target/riscv/zbc64.c: Likewise. * gcc.target/riscv/zbkb32.c: Likewise. * gcc.target/riscv/zbkb64.c: Likewise. * gcc.target/riscv/zbkc32.c: Likewise. * gcc.target/riscv/zbkc64.c: Likewise. * gcc.target/riscv/zbkx32.c: Likewise. * gcc.target/riscv/zbkx64.c: Likewise. * gcc.target/riscv/zfa-fleq-fltq.c: Likewise. * gcc.target/riscv/zfa-fli-zfh.c: Likewise. * gcc.target/riscv/zfa-fli.c: Likewise. * gcc.target/riscv/zknd64.c: Likewise. * gcc.target/riscv/zksed32.c: Likewise. * gcc.target/riscv/zksed64.c: Likewise. * gcc.target/riscv/zksh32.c: Likewise. * gcc.target/riscv/zksh64.c: Likewise. * gcc.target/riscv/_Float16-soft-1.c: Likewise. * gcc.target/riscv/_Float16-zfhmin-1.c: Likewise. * gcc.target/riscv/_Float16-zfhmin-2.c: Likewise. * gcc.target/riscv/_Float16-zfhmin-3.c: Likewise. * gcc.target/riscv/_Float16-zhinxmin-1.c: Likewise. * gcc.target/riscv/_Float16-zhinxmin-2.c: Likewise. * gcc.target/riscv/_Float16-zhinxmin-3.c: Likewise. * gcc.target/riscv/fle-ieee.c: Likewise. * gcc.target/riscv/fle-snan.c: Likewise. * gcc.target/riscv/flef-ieee.c: Likewise. * gcc.target/riscv/flef-snan.c: Likewise. * gcc.target/riscv/flt-ieee.c: Likewise. * gcc.target/riscv/flt-snan.c: Likewise. * gcc.target/riscv/fltf-ieee.c: Likewise. * gcc.target/riscv/fltf-snan.c: Likewise. * gcc.target/riscv/interrupt-1.c: Likewise. * gcc.target/riscv/interrupt-mmode.c: Likewise. * gcc.target/riscv/interrupt-smode.c: Likewise. * gcc.target/riscv/interrupt-umode.c: Likewise. * gcc.target/riscv/pr106888.c: Likewise. * gcc.target/riscv/pr89835.c: Likewise. * gcc.target/riscv/shift-and-1.c: Likewise. * gcc.target/riscv/shift-and-2.c: Likewise. * gcc.target/riscv/shift-shift-2.c: Likewise. * gcc.target/riscv/shift-shift-4.c: Likewise. * gcc.target/riscv/shift-shift-5.c: Likewise. * gcc.target/riscv/shorten-memrefs-7.c: Likewise. * gcc.target/riscv/sign-extend.c: Likewise. * gcc.target/riscv/switch-qi.c: Likewise. * gcc.target/riscv/switch-si.c: Likewise. * gcc.target/riscv/xtheadbb-ext-1.c: Likewise. * gcc.target/riscv/xtheadbb-ext.c: Likewise. * gcc.target/riscv/xtheadbb-extu-1.c: Likewise. * gcc.target/riscv/xtheadbb-extu.c: Likewise. * gcc.target/riscv/xtheadbb-strlen.c: Likewise. * gcc.target/riscv/xtheadbs-tst.c: Likewise. * gcc.target/riscv/xtheadfmv-fmv.c: Likewise. * gcc.target/riscv/xventanacondops-primitiveSemantics.c: Likewise. * gcc.target/riscv/zba-adduw.c: Likewise. * gcc.target/riscv/zba-shadd.c: Likewise. * gcc.target/riscv/zba-slliuw.c: Likewise. * gcc.target/riscv/zba-zextw.c: Likewise. * gcc.target/riscv/zbb-min-max-02.c: Likewise. * gcc.target/riscv/zbb-min-max-03.c: Likewise. * gcc.target/riscv/zbb-rol-ror-01.c: Likewise. * gcc.target/riscv/zbb-rol-ror-03.c: Likewise. * gcc.target/riscv/zbb-rol-ror-04.c: Likewise. * gcc.target/riscv/zbb-rol-ror-05.c: Likewise. * gcc.target/riscv/zbb-rol-ror-06.c: Likewise. * gcc.target/riscv/zbb-rol-ror-07.c: Likewise. * gcc.target/riscv/zbb-rol-ror-08.c: Likewise. * gcc.target/riscv/zbb-rol-ror-09.c: Likewise. * gcc.target/riscv/zbb-strlen.c: Likewise. * gcc.target/riscv/zbb_32_bswap-1.c: Likewise. * gcc.target/riscv/zbb_32_bswap-2.c: Likewise. * gcc.target/riscv/zbb_bswap-1.c: Likewise. * gcc.target/riscv/zbb_bswap-2.c: Likewise. * gcc.target/riscv/zbs-bclr.c: Likewise. * gcc.target/riscv/zbs-bext-02.c: Likewise. * gcc.target/riscv/zbs-bext.c: Likewise. * gcc.target/riscv/zbs-binv.c: Likewise. * gcc.target/riscv/zbs-bset.c: Likewise. * gcc.target/riscv/zero-scratch-regs-2.c: Likewise. * gcc.target/riscv/zicond-primitiveSemantics.c: Likewise. * gcc.target/riscv/zicond-primitiveSemantics_return_0_imm.c: Likewise. * gcc.target/riscv/zicond-primitiveSemantics_return_imm_imm.c: Likewise. * gcc.target/riscv/zicond-primitiveSemantics_return_imm_reg.c: Likewise. * gcc.target/riscv/zicond-primitiveSemantics_return_reg_reg.c: Likewise. --- diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-soft-1.c b/gcc/testsuite/gcc.target/riscv/_Float16-soft-1.c index 0622588fdb93..ba56dda21ec4 100644 --- a/gcc/testsuite/gcc.target/riscv/_Float16-soft-1.c +++ b/gcc/testsuite/gcc.target/riscv/_Float16-soft-1.c @@ -6,4 +6,4 @@ _Float16 test_soft_move (_Float16 a, _Float16 b) return b; } -/* { dg-final { scan-assembler-not "fmv.h" } } */ +/* { dg-final { scan-assembler-not {\mfmv\.h\M} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-soft-2.c b/gcc/testsuite/gcc.target/riscv/_Float16-soft-2.c index 3d37823fa4d1..e1a841e205ff 100644 --- a/gcc/testsuite/gcc.target/riscv/_Float16-soft-2.c +++ b/gcc/testsuite/gcc.target/riscv/_Float16-soft-2.c @@ -7,7 +7,7 @@ _Float16 test_soft_add (_Float16 a, _Float16 b) /* { dg-final { scan-assembler-times "call\t__extendhfsf2" 2 } } */ return a + b; /* { dg-final { scan-assembler-not "call\t__addhf3" } } */ - /* { dg-final { scan-assembler-times "fadd.s" 1 } } */ + /* { dg-final { scan-assembler-times {\mfadd\.s\M} 1 } } */ /* { dg-final { scan-assembler-times "call\t__truncsfhf2" 1 } } */ } diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-soft-3.c b/gcc/testsuite/gcc.target/riscv/_Float16-soft-3.c index ecce364e3107..66c5a369424a 100644 --- a/gcc/testsuite/gcc.target/riscv/_Float16-soft-3.c +++ b/gcc/testsuite/gcc.target/riscv/_Float16-soft-3.c @@ -7,6 +7,6 @@ int test_soft_compare (_Float16 a, _Float16 b) /* { dg-final { scan-assembler-times "call\t__extendhfsf2" 2 } } */ return a > b; /* { dg-final { scan-assembler-not "call\t__gthf2" } } */ - /* { dg-final { scan-assembler-times "fgt.s" 1 } } */ + /* { dg-final { scan-assembler-times {\mfgt\.s\M} 1 } } */ } diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-zfh-1.c b/gcc/testsuite/gcc.target/riscv/_Float16-zfh-1.c index 98908dccbb38..433945507110 100644 --- a/gcc/testsuite/gcc.target/riscv/_Float16-zfh-1.c +++ b/gcc/testsuite/gcc.target/riscv/_Float16-zfh-1.c @@ -3,6 +3,6 @@ _Float16 foo1 (_Float16 a, _Float16 b) { - /* { dg-final { scan-assembler-times "fmv.h" 1 } } */ + /* { dg-final { scan-assembler-times {\mfmv\.h\M} 1 } } */ return b; } diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-zfh-2.c b/gcc/testsuite/gcc.target/riscv/_Float16-zfh-2.c index 58bfa6b41985..3f9ecedb15c8 100644 --- a/gcc/testsuite/gcc.target/riscv/_Float16-zfh-2.c +++ b/gcc/testsuite/gcc.target/riscv/_Float16-zfh-2.c @@ -3,6 +3,6 @@ _Float16 foo1 (_Float16 a, _Float16 b) { - /* { dg-final { scan-assembler-times "fadd.h" 1 } } */ + /* { dg-final { scan-assembler-times {\mfadd\.h\M} 1 } } */ return a + b; } diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-zfh-3.c b/gcc/testsuite/gcc.target/riscv/_Float16-zfh-3.c index 128b4e53f27c..b70b7118bd4c 100644 --- a/gcc/testsuite/gcc.target/riscv/_Float16-zfh-3.c +++ b/gcc/testsuite/gcc.target/riscv/_Float16-zfh-3.c @@ -3,6 +3,6 @@ int foo1 (_Float16 a, _Float16 b) { - /* { dg-final { scan-assembler-times "fgt.h" 1 } } */ + /* { dg-final { scan-assembler-times {\mfgt\.h\M} 1 } } */ return a > b; } diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-zfhmin-1.c b/gcc/testsuite/gcc.target/riscv/_Float16-zfhmin-1.c index 631a049f52f5..8fcc51bad55a 100644 --- a/gcc/testsuite/gcc.target/riscv/_Float16-zfhmin-1.c +++ b/gcc/testsuite/gcc.target/riscv/_Float16-zfhmin-1.c @@ -3,7 +3,7 @@ _Float16 foo1 (_Float16 a, _Float16 b) { - /* { dg-final { scan-assembler-not "fmv.h" } } */ - /* { dg-final { scan-assembler-times "fmv.s" 1 } } */ + /* { dg-final { scan-assembler-not {\mfmv\.h\M} } } */ + /* { dg-final { scan-assembler-times {\mfmv\.s\M} 1 } } */ return b; } diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-zfhmin-2.c b/gcc/testsuite/gcc.target/riscv/_Float16-zfhmin-2.c index 06c85eb797de..f9b615ce3a0d 100644 --- a/gcc/testsuite/gcc.target/riscv/_Float16-zfhmin-2.c +++ b/gcc/testsuite/gcc.target/riscv/_Float16-zfhmin-2.c @@ -3,7 +3,7 @@ _Float16 foo1 (_Float16 a, _Float16 b) { - /* { dg-final { scan-assembler-not "fadd.h" } } */ - /* { dg-final { scan-assembler-times "fadd.s" 1 } } */ + /* { dg-final { scan-assembler-not {\mfadd\.h\M} } } */ + /* { dg-final { scan-assembler-times {\mfadd\.s\M} 1 } } */ return a + b; } diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-zfhmin-3.c b/gcc/testsuite/gcc.target/riscv/_Float16-zfhmin-3.c index 28960d602458..2a35006cfafe 100644 --- a/gcc/testsuite/gcc.target/riscv/_Float16-zfhmin-3.c +++ b/gcc/testsuite/gcc.target/riscv/_Float16-zfhmin-3.c @@ -3,7 +3,7 @@ int foo1 (_Float16 a, _Float16 b) { - /* { dg-final { scan-assembler-not "fgt.h" } } */ - /* { dg-final { scan-assembler-times "fgt.s" 1 } } */ + /* { dg-final { scan-assembler-not {\mfgt\.h\M} } } */ + /* { dg-final { scan-assembler-times {\mfgt\.s\M} 1 } } */ return a > b; } diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-1.c b/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-1.c index fa049db5b932..4c57890afd0c 100644 --- a/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-1.c +++ b/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-1.c @@ -3,8 +3,8 @@ _Float16 foo1 (_Float16 a, _Float16 b) { - /* { dg-final { scan-assembler-not "fmv.h" } } */ - /* { dg-final { scan-assembler-not "fmv.s" } } */ + /* { dg-final { scan-assembler-not {\mfmv\.h\M} } } */ + /* { dg-final { scan-assembler-not {\mfmv\.s\M} } } */ /* { dg-final { scan-assembler-times "mv\ta0" 1 } } */ return b; } diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-2.c b/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-2.c index 17f45a938d55..31aa40d7e8e5 100644 --- a/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-2.c +++ b/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-2.c @@ -3,7 +3,7 @@ _Float16 foo1 (_Float16 a, _Float16 b) { - /* { dg-final { scan-assembler-not "fadd.h" } } */ + /* { dg-final { scan-assembler-not {\mfadd\.h\M} } } */ /* { dg-final { scan-assembler-not "fadd.s fa" } } */ /* { dg-final { scan-assembler-times "fadd.s a" 1 } } */ return a + b; diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-3.c b/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-3.c index 939b37873836..230c0229413d 100644 --- a/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-3.c +++ b/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-3.c @@ -3,7 +3,7 @@ int foo1 (_Float16 a, _Float16 b) { - /* { dg-final { scan-assembler-not "fgt.h" } } */ + /* { dg-final { scan-assembler-not {\mfgt\.h\M} } } */ /* { dg-final { scan-assembler-not "fgt.s fa" } } */ /* { dg-final { scan-assembler-times "fgt.s a" 1 } } */ return a > b; diff --git a/gcc/testsuite/gcc.target/riscv/and-extend-1.c b/gcc/testsuite/gcc.target/riscv/and-extend-1.c index a270d2873740..2fe4da3e4c50 100644 --- a/gcc/testsuite/gcc.target/riscv/and-extend-1.c +++ b/gcc/testsuite/gcc.target/riscv/and-extend-1.c @@ -23,8 +23,8 @@ foo3(unsigned int a, unsigned int* ptr) ptr[1] &= 0xffff; } -/* { dg-final { scan-assembler-times "zext.w" 1 } } */ -/* { dg-final { scan-assembler-times "zext.h" 2 } } */ -/* { dg-final { scan-assembler-times "lwu" 1 } } */ -/* { dg-final { scan-assembler-times "lhu" 2 } } */ +/* { dg-final { scan-assembler-times {\mzext\.w\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mzext\.h\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mlwu} 1 } } */ +/* { dg-final { scan-assembler-times {\mlhu} 2 } } */ /* { dg-final { scan-assembler-not "and\t" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/and-extend-2.c b/gcc/testsuite/gcc.target/riscv/and-extend-2.c index fe639cd1e821..e5a9cf62351e 100644 --- a/gcc/testsuite/gcc.target/riscv/and-extend-2.c +++ b/gcc/testsuite/gcc.target/riscv/and-extend-2.c @@ -23,6 +23,6 @@ foo3(unsigned int a, unsigned int* ptr) ptr[1] &= 0xffff; } -/* { dg-final { scan-assembler-times "zext.h" 2 } } */ -/* { dg-final { scan-assembler-times "lhu" 2 } } */ +/* { dg-final { scan-assembler-times {\mzext\.h\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mlhu} 2 } } */ /* { dg-final { scan-assembler-not "and\t" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/fle-ieee.c b/gcc/testsuite/gcc.target/riscv/fle-ieee.c index af9d503b1ecc..e55331f925d6 100644 --- a/gcc/testsuite/gcc.target/riscv/fle-ieee.c +++ b/gcc/testsuite/gcc.target/riscv/fle-ieee.c @@ -9,4 +9,4 @@ fle (double x, double y) } /* { dg-final { scan-assembler "\tfrflags\t(\[^\n\]*)\n\tfle\\.d\t\[^\n\]*\n\tfsflags\t\\1\n" } } */ -/* { dg-final { scan-assembler-not "snez" } } */ +/* { dg-final { scan-assembler-not {\msnez} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/fle-snan.c b/gcc/testsuite/gcc.target/riscv/fle-snan.c index 0579d93109b3..f40bb2cbf662 100644 --- a/gcc/testsuite/gcc.target/riscv/fle-snan.c +++ b/gcc/testsuite/gcc.target/riscv/fle-snan.c @@ -9,4 +9,4 @@ fle (double x, double y) } /* { dg-final { scan-assembler "\tfrflags\t(\[^\n\]*)\n\tfle\\.d\t\[^,\]*,(\[^,\]*),(\[^,\]*)\n\tfsflags\t\\1\n\tfeq\\.d\tzero,\\2,\\3\n" } } */ -/* { dg-final { scan-assembler-not "snez" } } */ +/* { dg-final { scan-assembler-not {\msnez} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/flef-ieee.c b/gcc/testsuite/gcc.target/riscv/flef-ieee.c index e2d6b0d91b55..f3e7e7d75d6c 100644 --- a/gcc/testsuite/gcc.target/riscv/flef-ieee.c +++ b/gcc/testsuite/gcc.target/riscv/flef-ieee.c @@ -9,4 +9,4 @@ flef (float x, float y) } /* { dg-final { scan-assembler "\tfrflags\t(\[^\n\]*)\n\tfle\\.s\t\[^\n\]*\n\tfsflags\t\\1\n" } } */ -/* { dg-final { scan-assembler-not "snez" } } */ +/* { dg-final { scan-assembler-not {\msnez} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/flef-snan.c b/gcc/testsuite/gcc.target/riscv/flef-snan.c index 2d2c5b9e79f8..ef75b3523057 100644 --- a/gcc/testsuite/gcc.target/riscv/flef-snan.c +++ b/gcc/testsuite/gcc.target/riscv/flef-snan.c @@ -9,4 +9,4 @@ flef (float x, float y) } /* { dg-final { scan-assembler "\tfrflags\t(\[^\n\]*)\n\tfle\\.s\t\[^,\]*,(\[^,\]*),(\[^,\]*)\n\tfsflags\t\\1\n\tfeq\\.s\tzero,\\2,\\3\n" } } */ -/* { dg-final { scan-assembler-not "snez" } } */ +/* { dg-final { scan-assembler-not {\msnez} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/flt-ieee.c b/gcc/testsuite/gcc.target/riscv/flt-ieee.c index 7d7aae303e6c..c40a0fc11806 100644 --- a/gcc/testsuite/gcc.target/riscv/flt-ieee.c +++ b/gcc/testsuite/gcc.target/riscv/flt-ieee.c @@ -9,4 +9,4 @@ flt (double x, double y) } /* { dg-final { scan-assembler "\tfrflags\t(\[^\n\]*)\n\tflt\\.d\t\[^\n\]*\n\tfsflags\t\\1\n" } } */ -/* { dg-final { scan-assembler-not "snez" } } */ +/* { dg-final { scan-assembler-not {\msnez} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/flt-snan.c b/gcc/testsuite/gcc.target/riscv/flt-snan.c index ff4c4e9ac8d8..c958ec018422 100644 --- a/gcc/testsuite/gcc.target/riscv/flt-snan.c +++ b/gcc/testsuite/gcc.target/riscv/flt-snan.c @@ -9,4 +9,4 @@ flt (double x, double y) } /* { dg-final { scan-assembler "\tfrflags\t(\[^\n\]*)\n\tflt\\.d\t\[^,\]*,(\[^,\]*),(\[^,\]*)\n\tfsflags\t\\1\n\tfeq\\.d\tzero,\\2,\\3\n" } } */ -/* { dg-final { scan-assembler-not "snez" } } */ +/* { dg-final { scan-assembler-not {\msnez} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/fltf-ieee.c b/gcc/testsuite/gcc.target/riscv/fltf-ieee.c index ede076eea360..a9c0805037e6 100644 --- a/gcc/testsuite/gcc.target/riscv/fltf-ieee.c +++ b/gcc/testsuite/gcc.target/riscv/fltf-ieee.c @@ -9,4 +9,4 @@ fltf (float x, float y) } /* { dg-final { scan-assembler "\tfrflags\t(\[^\n\]*)\n\tflt\\.s\t\[^\n\]*\n\tfsflags\t\\1\n" } } */ -/* { dg-final { scan-assembler-not "snez" } } */ +/* { dg-final { scan-assembler-not {\msnez} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/fltf-snan.c b/gcc/testsuite/gcc.target/riscv/fltf-snan.c index d29d786f7f05..34a51e3e800a 100644 --- a/gcc/testsuite/gcc.target/riscv/fltf-snan.c +++ b/gcc/testsuite/gcc.target/riscv/fltf-snan.c @@ -9,4 +9,4 @@ fltf (float x, float y) } /* { dg-final { scan-assembler "\tfrflags\t(\[^\n\]*)\n\tflt\\.s\t\[^,\]*,(\[^,\]*),(\[^,\]*)\n\tfsflags\t\\1\n\tfeq\\.s\tzero,\\2,\\3\n" } } */ -/* { dg-final { scan-assembler-not "snez" } } */ +/* { dg-final { scan-assembler-not {\msnez} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/interrupt-1.c b/gcc/testsuite/gcc.target/riscv/interrupt-1.c index d85eb980e16e..506aef4adc43 100644 --- a/gcc/testsuite/gcc.target/riscv/interrupt-1.c +++ b/gcc/testsuite/gcc.target/riscv/interrupt-1.c @@ -5,4 +5,4 @@ void __attribute__ ((interrupt)) foo (void) { } -/* { dg-final { scan-assembler "mret" } } */ +/* { dg-final { scan-assembler {\mmret} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/interrupt-mmode.c b/gcc/testsuite/gcc.target/riscv/interrupt-mmode.c index 50d54a0cf340..7b7f0a7a7c68 100644 --- a/gcc/testsuite/gcc.target/riscv/interrupt-mmode.c +++ b/gcc/testsuite/gcc.target/riscv/interrupt-mmode.c @@ -5,4 +5,4 @@ void __attribute__ ((interrupt ("machine"))) foo (void) { } -/* { dg-final { scan-assembler "mret" } } */ +/* { dg-final { scan-assembler {\mmret} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/interrupt-smode.c b/gcc/testsuite/gcc.target/riscv/interrupt-smode.c index 973a9b1cac54..ef0e59b45977 100644 --- a/gcc/testsuite/gcc.target/riscv/interrupt-smode.c +++ b/gcc/testsuite/gcc.target/riscv/interrupt-smode.c @@ -5,4 +5,4 @@ void __attribute__ ((interrupt ("supervisor"))) foo (void) { } -/* { dg-final { scan-assembler "sret" } } */ +/* { dg-final { scan-assembler {\msret} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/interrupt-umode.c b/gcc/testsuite/gcc.target/riscv/interrupt-umode.c index 7fcef755b0c7..042abf02ad29 100644 --- a/gcc/testsuite/gcc.target/riscv/interrupt-umode.c +++ b/gcc/testsuite/gcc.target/riscv/interrupt-umode.c @@ -5,4 +5,4 @@ void __attribute__ ((interrupt ("user"))) foo (void) { } -/* { dg-final { scan-assembler "uret" } } */ +/* { dg-final { scan-assembler {\muret} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/pr106888.c b/gcc/testsuite/gcc.target/riscv/pr106888.c index 77fb8e5b79c6..739d5d7e5efe 100644 --- a/gcc/testsuite/gcc.target/riscv/pr106888.c +++ b/gcc/testsuite/gcc.target/riscv/pr106888.c @@ -8,5 +8,5 @@ ctz (int i) return res&0xffff; } -/* { dg-final { scan-assembler-times "ctzw" 1 } } */ -/* { dg-final { scan-assembler-not "andi" } } */ +/* { dg-final { scan-assembler-times {\mctzw} 1 } } */ +/* { dg-final { scan-assembler-not {\mandi} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/pr108987.c b/gcc/testsuite/gcc.target/riscv/pr108987.c index 6179c7e13a45..be9cd92dbfad 100644 --- a/gcc/testsuite/gcc.target/riscv/pr108987.c +++ b/gcc/testsuite/gcc.target/riscv/pr108987.c @@ -6,4 +6,4 @@ unsigned long long f5(unsigned long long i) return i * 0x0202020202020202ULL; } -/* { dg-final { scan-assembler-times "mul" 1 } } */ +/* { dg-final { scan-assembler-times {\mmul} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/pr89835.c b/gcc/testsuite/gcc.target/riscv/pr89835.c index ab190e11b608..b7adc7c54f8f 100644 --- a/gcc/testsuite/gcc.target/riscv/pr89835.c +++ b/gcc/testsuite/gcc.target/riscv/pr89835.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* Verify that relaxed atomic stores use simple store instuctions. */ -/* { dg-final { scan-assembler-not "amoswap" } } */ +/* { dg-final { scan-assembler-not {\mamoswap} } } */ void foo(int bar, int baz) diff --git a/gcc/testsuite/gcc.target/riscv/ret-1.c b/gcc/testsuite/gcc.target/riscv/ret-1.c index 28133aa4226e..92795958f5c9 100644 --- a/gcc/testsuite/gcc.target/riscv/ret-1.c +++ b/gcc/testsuite/gcc.target/riscv/ret-1.c @@ -37,5 +37,5 @@ core_list_find(list_head *list, list_data *info) /* There is only one legitimate unconditional jump, so test for that, which will catch the case where bb-reorder leaves a jump to a ret in the IL. */ -/* { dg-final { scan-assembler-times "jump" 1 } } */ +/* { dg-final { scan-assembler-times {\mjump} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-1.c index 14201e1f7e06..64007ee67997 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-1.c @@ -8,5 +8,5 @@ f (int * __restrict dst, int * __restrict op1, int * __restrict op2, int count) dst[i] = op1[i] + op2[i]; } -/* { dg-final { scan-assembler-not "lw" } } */ -/* { dg-final { scan-assembler-not "sw" } } */ +/* { dg-final { scan-assembler-not {\mlw} } } */ +/* { dg-final { scan-assembler-not {\msw} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-2.c index 812584e9d25f..a82f34e0464c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-2.c @@ -8,5 +8,5 @@ f (int * __restrict dst, int * __restrict op1, int * __restrict op2, int count) dst[i] = op1[i] + op2[i]; } -/* { dg-final { scan-assembler-not "lw" } } */ -/* { dg-final { scan-assembler-not "sw" } } */ +/* { dg-final { scan-assembler-not {\mlw} } } */ +/* { dg-final { scan-assembler-not {\msw} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/shift-and-1.c b/gcc/testsuite/gcc.target/riscv/shift-and-1.c index 429ab84f9df6..2d483d06baa8 100644 --- a/gcc/testsuite/gcc.target/riscv/shift-and-1.c +++ b/gcc/testsuite/gcc.target/riscv/shift-and-1.c @@ -8,4 +8,4 @@ sub1 (int i, int j) { return i << (j & 0x1f); } -/* { dg-final { scan-assembler-not "andi" } } */ +/* { dg-final { scan-assembler-not {\mandi} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/shift-and-2.c b/gcc/testsuite/gcc.target/riscv/shift-and-2.c index ee9925b74985..9b4ca11fcbab 100644 --- a/gcc/testsuite/gcc.target/riscv/shift-and-2.c +++ b/gcc/testsuite/gcc.target/riscv/shift-and-2.c @@ -57,5 +57,5 @@ sub9 (unsigned i, unsigned j) { return (i >> 10) & j; } -/* { dg-final { scan-assembler-not "andi" } } */ -/* { dg-final { scan-assembler-not "sext.w" } } */ +/* { dg-final { scan-assembler-not {\mandi} } } */ +/* { dg-final { scan-assembler-not {\msext\.w\M} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/shift-shift-1.c b/gcc/testsuite/gcc.target/riscv/shift-shift-1.c index 462e532e1f1e..bae6c8a40168 100644 --- a/gcc/testsuite/gcc.target/riscv/shift-shift-1.c +++ b/gcc/testsuite/gcc.target/riscv/shift-shift-1.c @@ -14,5 +14,5 @@ sub2 (unsigned int i) { return (i << 20) >> 20; } -/* { dg-final { scan-assembler-times "slli" 2 } } */ -/* { dg-final { scan-assembler-times "srli" 2 } } */ +/* { dg-final { scan-assembler-times {\mslli} 2 } } */ +/* { dg-final { scan-assembler-times {\msrli} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/shift-shift-2.c b/gcc/testsuite/gcc.target/riscv/shift-shift-2.c index bc8c4ef38289..3b0c9d5dfb4d 100644 --- a/gcc/testsuite/gcc.target/riscv/shift-shift-2.c +++ b/gcc/testsuite/gcc.target/riscv/shift-shift-2.c @@ -36,8 +36,8 @@ sub5 (unsigned int i) j = i - j; return j; } -/* { dg-final { scan-assembler-times "slli" 5 } } */ -/* { dg-final { scan-assembler-times "srli" 5 } } */ +/* { dg-final { scan-assembler-times {\mslli} 5 } } */ +/* { dg-final { scan-assembler-times {\msrli} 5 } } */ /* { dg-final { scan-assembler-times ",40" 2 } } */ /* For sub5 test */ -/* { dg-final { scan-assembler-not "slliw" } } */ -/* { dg-final { scan-assembler-not "srliw" } } */ +/* { dg-final { scan-assembler-not {\mslliw} } } */ +/* { dg-final { scan-assembler-not {\msrliw} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/shift-shift-3.c b/gcc/testsuite/gcc.target/riscv/shift-shift-3.c index 16999b02796c..d9154a12c589 100644 --- a/gcc/testsuite/gcc.target/riscv/shift-shift-3.c +++ b/gcc/testsuite/gcc.target/riscv/shift-shift-3.c @@ -15,5 +15,5 @@ sub2 (unsigned long i) { return (i >> 63) << 63; } -/* { dg-final { scan-assembler-times "slli" 2 } } */ -/* { dg-final { scan-assembler-times "srli" 2 } } */ +/* { dg-final { scan-assembler-times {\mslli} 2 } } */ +/* { dg-final { scan-assembler-times {\msrli} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/shift-shift-4.c b/gcc/testsuite/gcc.target/riscv/shift-shift-4.c index bc7bca10e6f3..c479649a1853 100644 --- a/gcc/testsuite/gcc.target/riscv/shift-shift-4.c +++ b/gcc/testsuite/gcc.target/riscv/shift-shift-4.c @@ -11,4 +11,4 @@ sub (int i) i &= 0x7fffffff; return i > 0x7f800000; } -/* { dg-final { scan-assembler-not "srli" } } */ +/* { dg-final { scan-assembler-not {\msrli} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/shift-shift-5.c b/gcc/testsuite/gcc.target/riscv/shift-shift-5.c index ed8e7b3f1cb1..d012866c2adc 100644 --- a/gcc/testsuite/gcc.target/riscv/shift-shift-5.c +++ b/gcc/testsuite/gcc.target/riscv/shift-shift-5.c @@ -18,4 +18,4 @@ sub (long l) u.l = l; return u.s.b; } -/* { dg-final { scan-assembler "srliw" } } */ +/* { dg-final { scan-assembler {\msrliw} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-7.c b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-7.c index 476d079679fe..ba7b783e8d28 100644 --- a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-7.c +++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-7.c @@ -44,4 +44,4 @@ load2r (long long *array) return a; } -/* { dg-final { scan-assembler-not "addi" } } */ +/* { dg-final { scan-assembler-not {\maddi} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sign-extend.c b/gcc/testsuite/gcc.target/riscv/sign-extend.c index 6f8401948330..47be57dc88ec 100644 --- a/gcc/testsuite/gcc.target/riscv/sign-extend.c +++ b/gcc/testsuite/gcc.target/riscv/sign-extend.c @@ -69,13 +69,13 @@ foo11 (unsigned x) return x & (15 + x); } -/* { dg-final { scan-assembler-times "subw" 2 } } */ -/* { dg-final { scan-assembler-times "addw" 1 } } */ -/* { dg-final { scan-assembler-times "addiw" 1 } } */ -/* { dg-final { scan-assembler-times "mulw" 2 } } */ -/* { dg-final { scan-assembler-times "divw" 1 } } */ -/* { dg-final { scan-assembler-times "divuw" 1 } } */ -/* { dg-final { scan-assembler-times "remw" 1 } } */ -/* { dg-final { scan-assembler-times "remuw" 1 } } */ -/* { dg-final { scan-assembler-times "negw" 1 } } */ -/* { dg-final { scan-assembler-not "sext.w" } } */ +/* { dg-final { scan-assembler-times {\msubw} 2 } } */ +/* { dg-final { scan-assembler-times {\maddw} 1 } } */ +/* { dg-final { scan-assembler-times {\maddiw} 1 } } */ +/* { dg-final { scan-assembler-times {\mmulw} 2 } } */ +/* { dg-final { scan-assembler-times {\mdivw} 1 } } */ +/* { dg-final { scan-assembler-times {\mdivuw} 1 } } */ +/* { dg-final { scan-assembler-times {\mremw} 1 } } */ +/* { dg-final { scan-assembler-times {\mremuw} 1 } } */ +/* { dg-final { scan-assembler-times {\mnegw} 1 } } */ +/* { dg-final { scan-assembler-not {\msext\.w\M} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/switch-qi.c b/gcc/testsuite/gcc.target/riscv/switch-qi.c index e39219bea363..9126e0a10b20 100644 --- a/gcc/testsuite/gcc.target/riscv/switch-qi.c +++ b/gcc/testsuite/gcc.target/riscv/switch-qi.c @@ -12,4 +12,4 @@ void foo(signed char x) { case 4: asdf(14); break; } } -/* { dg-final { scan-assembler-not "andi" } } */ +/* { dg-final { scan-assembler-not {\mandi} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/switch-si.c b/gcc/testsuite/gcc.target/riscv/switch-si.c index c68f98d04e6c..e76c2aa088d0 100644 --- a/gcc/testsuite/gcc.target/riscv/switch-si.c +++ b/gcc/testsuite/gcc.target/riscv/switch-si.c @@ -12,4 +12,4 @@ void foo(int x) { case 4: asdf(14); break; } } -/* { dg-final { scan-assembler-not "srli" } } */ +/* { dg-final { scan-assembler-not {\msrli} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbb-ext-1.c b/gcc/testsuite/gcc.target/riscv/xtheadbb-ext-1.c index 02f6ec1417de..04b823210455 100644 --- a/gcc/testsuite/gcc.target/riscv/xtheadbb-ext-1.c +++ b/gcc/testsuite/gcc.target/riscv/xtheadbb-ext-1.c @@ -63,5 +63,5 @@ char sext8_16(short s16) return s16; } -/* { dg-final { scan-assembler-not "slli" } } */ -/* { dg-final { scan-assembler-not "srli" } } */ +/* { dg-final { scan-assembler-not {\mslli} } } */ +/* { dg-final { scan-assembler-not {\msrli} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbb-ext.c b/gcc/testsuite/gcc.target/riscv/xtheadbb-ext.c index 60fb7d44e39e..121d9697d714 100644 --- a/gcc/testsuite/gcc.target/riscv/xtheadbb-ext.c +++ b/gcc/testsuite/gcc.target/riscv/xtheadbb-ext.c @@ -17,4 +17,4 @@ foo (struct bar *s) } /* { dg-final { scan-assembler "th.ext\t" } } */ -/* { dg-final { scan-assembler-not "andi" } } */ +/* { dg-final { scan-assembler-not {\mandi} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbb-extu-1.c b/gcc/testsuite/gcc.target/riscv/xtheadbb-extu-1.c index 01e3eda7df2f..b92445c51326 100644 --- a/gcc/testsuite/gcc.target/riscv/xtheadbb-extu-1.c +++ b/gcc/testsuite/gcc.target/riscv/xtheadbb-extu-1.c @@ -63,5 +63,5 @@ unsigned char zext8_16(unsigned short u16) return u16; } -/* { dg-final { scan-assembler-not "slli" } } */ -/* { dg-final { scan-assembler-not "srli" } } */ +/* { dg-final { scan-assembler-not {\mslli} } } */ +/* { dg-final { scan-assembler-not {\msrli} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbb-extu.c b/gcc/testsuite/gcc.target/riscv/xtheadbb-extu.c index e0492f1f5adc..fca9b7e438a2 100644 --- a/gcc/testsuite/gcc.target/riscv/xtheadbb-extu.c +++ b/gcc/testsuite/gcc.target/riscv/xtheadbb-extu.c @@ -17,6 +17,6 @@ foo (struct bar *s) } /* { dg-final { scan-assembler "th.extu\t" } } */ -/* { dg-final { scan-assembler-not "andi" } } */ -/* { dg-final { scan-assembler-not "slli" } } */ -/* { dg-final { scan-assembler-not "srli" } } */ +/* { dg-final { scan-assembler-not {\mandi} } } */ +/* { dg-final { scan-assembler-not {\mslli} } } */ +/* { dg-final { scan-assembler-not {\msrli} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbb-strlen.c b/gcc/testsuite/gcc.target/riscv/xtheadbb-strlen.c index dbc8d1e7da7d..f243b6f1f4fd 100644 --- a/gcc/testsuite/gcc.target/riscv/xtheadbb-strlen.c +++ b/gcc/testsuite/gcc.target/riscv/xtheadbb-strlen.c @@ -13,7 +13,7 @@ my_str_len (const char *s) } /* { dg-final { scan-assembler "th.tstnbz\t" } } */ -/* { dg-final { scan-assembler-not "jalr" } } */ -/* { dg-final { scan-assembler-not "call" } } */ -/* { dg-final { scan-assembler-not "jr" } } */ -/* { dg-final { scan-assembler-not "tail" } } */ +/* { dg-final { scan-assembler-not {\mjalr} } } */ +/* { dg-final { scan-assembler-not {\mcall} } } */ +/* { dg-final { scan-assembler-not {\mjr} } } */ +/* { dg-final { scan-assembler-not {\mtail} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c b/gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c index 674cec09128a..f56d9ad344c9 100644 --- a/gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c +++ b/gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c @@ -10,4 +10,4 @@ foo1 (long i) } /* { dg-final { scan-assembler-times "th.tst\t" 1 } } */ -/* { dg-final { scan-assembler-not "andi" } } */ +/* { dg-final { scan-assembler-not {\mandi} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c b/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c index 89eb48bed1b9..9b4e23784480 100644 --- a/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c +++ b/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c @@ -14,9 +14,9 @@ d2ll (double d) return *(long long*)&d; } -/* { dg-final { scan-assembler "fmv.w.x" } } */ +/* { dg-final { scan-assembler {\mfmv\.w.x\M} } } */ /* { dg-final { scan-assembler "th.fmv.hw.x" } } */ -/* { dg-final { scan-assembler "fmv.x.w" } } */ +/* { dg-final { scan-assembler {\mfmv\.x.w\M} } } */ /* { dg-final { scan-assembler "th.fmv.x.hw" } } */ /* { dg-final { scan-assembler-not "\tsw\t" } } */ /* { dg-final { scan-assembler-not "\tfld\t" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics.c index 644ca12d6470..19bbcb6a5dfd 100644 --- a/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics.c +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics.c @@ -6,5 +6,5 @@ /* { dg-final { scan-assembler-times "vt\\.maskc\t" 6 } } */ /* { dg-final { scan-assembler-times "vt\\.maskcn\t" 6 } } */ -/* { dg-final { scan-assembler-not "beq" } } */ -/* { dg-final { scan-assembler-not "bne" } } */ +/* { dg-final { scan-assembler-not {\mbeq} } } */ +/* { dg-final { scan-assembler-not {\mbne} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zba-adduw.c b/gcc/testsuite/gcc.target/riscv/zba-adduw.c index 2ae03aee859d..a15ad7f9a55e 100644 --- a/gcc/testsuite/gcc.target/riscv/zba-adduw.c +++ b/gcc/testsuite/gcc.target/riscv/zba-adduw.c @@ -10,4 +10,4 @@ int foo(int n, unsigned char *arr, unsigned y){ return s; } -/* { dg-final { scan-assembler "add.uw" } } */ +/* { dg-final { scan-assembler {\madd\.uw\M} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zba-shNadd-01.c b/gcc/testsuite/gcc.target/riscv/zba-shNadd-01.c index bc97bc74539e..34dfd0ce9c74 100644 --- a/gcc/testsuite/gcc.target/riscv/zba-shNadd-01.c +++ b/gcc/testsuite/gcc.target/riscv/zba-shNadd-01.c @@ -15,6 +15,6 @@ long test_3(long a, long b) return a + (b << 3); } -/* { dg-final { scan-assembler-times "sh1add" 1 } } */ -/* { dg-final { scan-assembler-times "sh2add" 1 } } */ -/* { dg-final { scan-assembler-times "sh3add" 1 } } */ +/* { dg-final { scan-assembler-times {\msh1add} 1 } } */ +/* { dg-final { scan-assembler-times {\msh2add} 1 } } */ +/* { dg-final { scan-assembler-times {\msh3add} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zba-shNadd-02.c b/gcc/testsuite/gcc.target/riscv/zba-shNadd-02.c index 5f4b65f2d225..c40f2cb8d1e3 100644 --- a/gcc/testsuite/gcc.target/riscv/zba-shNadd-02.c +++ b/gcc/testsuite/gcc.target/riscv/zba-shNadd-02.c @@ -15,6 +15,6 @@ long test_3(long a, long b) return a + (b << 3); } -/* { dg-final { scan-assembler-times "sh1add" 1 } } */ -/* { dg-final { scan-assembler-times "sh2add" 1 } } */ -/* { dg-final { scan-assembler-times "sh3add" 1 } } */ +/* { dg-final { scan-assembler-times {\msh1add} 1 } } */ +/* { dg-final { scan-assembler-times {\msh2add} 1 } } */ +/* { dg-final { scan-assembler-times {\msh3add} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zba-shNadd-04.c b/gcc/testsuite/gcc.target/riscv/zba-shNadd-04.c index abed14910397..48e225d3f1e7 100644 --- a/gcc/testsuite/gcc.target/riscv/zba-shNadd-04.c +++ b/gcc/testsuite/gcc.target/riscv/zba-shNadd-04.c @@ -19,5 +19,5 @@ long long sub3(unsigned long long a, unsigned long long b) return (a + (b << 1)) & ~0u; } -/* { dg-final { scan-assembler-times "sh1add" 3 } } */ +/* { dg-final { scan-assembler-times {\msh1add} 3 } } */ /* { dg-final { scan-assembler-times "zext.w\t" 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zba-shNadd-07.c b/gcc/testsuite/gcc.target/riscv/zba-shNadd-07.c index 93da241c9b60..cd48664a4cd6 100644 --- a/gcc/testsuite/gcc.target/riscv/zba-shNadd-07.c +++ b/gcc/testsuite/gcc.target/riscv/zba-shNadd-07.c @@ -25,7 +25,7 @@ f4 (unsigned long i) return i * 1574; } -/* { dg-final { scan-assembler-times "sh2add" 2 } } */ -/* { dg-final { scan-assembler-times "sh1add" 1 } } */ -/* { dg-final { scan-assembler-times "slli" 3 } } */ -/* { dg-final { scan-assembler-times "mul" 2 } } */ +/* { dg-final { scan-assembler-times {\msh2add} 2 } } */ +/* { dg-final { scan-assembler-times {\msh1add} 1 } } */ +/* { dg-final { scan-assembler-times {\mslli} 3 } } */ +/* { dg-final { scan-assembler-times {\mmul} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zba-shadd.c b/gcc/testsuite/gcc.target/riscv/zba-shadd.c index 33da2530f3f5..61305d3a357d 100644 --- a/gcc/testsuite/gcc.target/riscv/zba-shadd.c +++ b/gcc/testsuite/gcc.target/riscv/zba-shadd.c @@ -10,4 +10,4 @@ unsigned long foo(unsigned int a, unsigned long b) } /* { dg-final { scan-assembler "sh2add.uw" } } */ -/* { dg-final { scan-assembler-not "zext" } } */ \ No newline at end of file +/* { dg-final { scan-assembler-not {\mzext} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zba-slliuw.c b/gcc/testsuite/gcc.target/riscv/zba-slliuw.c index cd3cf0eabc4e..c123bb5ece0f 100644 --- a/gcc/testsuite/gcc.target/riscv/zba-slliuw.c +++ b/gcc/testsuite/gcc.target/riscv/zba-slliuw.c @@ -9,4 +9,4 @@ foo (long i) } /* XXX: This pattern need combine improvement or intermediate instruction * from zbs. */ -/* { dg-final { scan-assembler "slli.uw" } } */ +/* { dg-final { scan-assembler {\mslli\.uw\M} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zba-zextw.c b/gcc/testsuite/gcc.target/riscv/zba-zextw.c index 271c186ad6d5..7da2a943b85b 100644 --- a/gcc/testsuite/gcc.target/riscv/zba-zextw.c +++ b/gcc/testsuite/gcc.target/riscv/zba-zextw.c @@ -8,4 +8,4 @@ foo (long i) return (long)(unsigned int)i; } /* XXX: This pattern require combine improvement. */ -/* { dg-final { scan-assembler-not "slli.uw" } } */ +/* { dg-final { scan-assembler-not {\mslli\.uw\M} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-01.c b/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-01.c index 89a30431ef16..a1f5f03cfc22 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-01.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-01.c @@ -17,6 +17,6 @@ unsigned long long foo3(unsigned long long rs1, unsigned long long rs2) return rs1 ^ ~rs2; } -/* { dg-final { scan-assembler-times "andn" 2 } } */ -/* { dg-final { scan-assembler-times "orn" 2 } } */ -/* { dg-final { scan-assembler-times "xnor" 2 } } */ \ No newline at end of file +/* { dg-final { scan-assembler-times {\mandn} 2 } } */ +/* { dg-final { scan-assembler-times {\morn} 2 } } */ +/* { dg-final { scan-assembler-times {\mxnor} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-02.c b/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-02.c index ef0dade47e6f..331bd332a56d 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-02.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-02.c @@ -17,6 +17,6 @@ unsigned int foo3(unsigned int rs1, unsigned int rs2) return rs1 ^ ~rs2; } -/* { dg-final { scan-assembler-times "andn" 2 } } */ -/* { dg-final { scan-assembler-times "orn" 2 } } */ -/* { dg-final { scan-assembler-times "xnor" 2 } } */ \ No newline at end of file +/* { dg-final { scan-assembler-times {\mandn} 2 } } */ +/* { dg-final { scan-assembler-times {\morn} 2 } } */ +/* { dg-final { scan-assembler-times {\mxnor} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbb-min-max-02.c b/gcc/testsuite/gcc.target/riscv/zbb-min-max-02.c index edfbf807d450..22bfb93ddddc 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-min-max-02.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-min-max-02.c @@ -8,7 +8,7 @@ int f(unsigned int* a) return *a * 3 > C ? C : *a * 3; } -/* { dg-final { scan-assembler-times "minu" 1 } } */ -/* { dg-final { scan-assembler-not "sext.w" } } */ -/* { dg-final { scan-assembler-not "zext.w" } } */ +/* { dg-final { scan-assembler-times {\mminu} 1 } } */ +/* { dg-final { scan-assembler-not {\msext\.w\M} } } */ +/* { dg-final { scan-assembler-not {\mzext\.w\M} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbb-min-max-03.c b/gcc/testsuite/gcc.target/riscv/zbb-min-max-03.c index 38c932b95800..769e876ced7a 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-min-max-03.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-min-max-03.c @@ -18,6 +18,6 @@ unsigned f3(unsigned x, unsigned y) { /* { dg-final { scan-assembler-not "li\t" } } */ /* { dg-final { scan-assembler-times "maxu\t" 1 } } */ /* { dg-final { scan-assembler-times "minu\t" 1 } } */ -/* { dg-final { scan-assembler-not "zext.w" } } */ -/* { dg-final { scan-assembler-not "sext.w" } } */ +/* { dg-final { scan-assembler-not {\mzext\.w\M} } } */ +/* { dg-final { scan-assembler-not {\msext\.w\M} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbb-min-max.c b/gcc/testsuite/gcc.target/riscv/zbb-min-max.c index ce054ddb37f2..2a5d9349b464 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-min-max.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-min-max.c @@ -26,7 +26,7 @@ foo4 (unsigned long i, unsigned long j) return i > j ? i : j; } -/* { dg-final { scan-assembler-times "min" 3 } } */ -/* { dg-final { scan-assembler-times "max" 3 } } */ -/* { dg-final { scan-assembler-times "minu" 1 } } */ -/* { dg-final { scan-assembler-times "maxu" 1 } } */ +/* { dg-final { scan-assembler-times {\mmin} 3 } } */ +/* { dg-final { scan-assembler-times {\mmax} 3 } } */ +/* { dg-final { scan-assembler-times {\mminu} 1 } } */ +/* { dg-final { scan-assembler-times {\mmaxu} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-01.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-01.c index 0a5b5e12eb2a..4f2ff7f54e64 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-01.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-01.c @@ -13,6 +13,6 @@ unsigned long foo2(unsigned long rs1, unsigned long rs2) return (rs1 >> shamt) | (rs1 << ((64 - shamt) & (64 - 1))); } -/* { dg-final { scan-assembler-times "rol" 2 } } */ -/* { dg-final { scan-assembler-times "ror" 2 } } */ -/* { dg-final { scan-assembler-not "and" } } */ \ No newline at end of file +/* { dg-final { scan-assembler-times {\mrol} 2 } } */ +/* { dg-final { scan-assembler-times {\mror} 2 } } */ +/* { dg-final { scan-assembler-not {\mand} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-02.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-02.c index d0d581358092..c24809234b60 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-02.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-02.c @@ -13,6 +13,6 @@ unsigned int foo2(unsigned int rs1, unsigned int rs2) return (rs1 >> shamt) | (rs1 << ((32 - shamt) & (32 - 1))); } -/* { dg-final { scan-assembler-times "rol" 2 } } */ -/* { dg-final { scan-assembler-times "ror" 2 } } */ -/* { dg-final { scan-assembler-not {and} { target { no-opts "-O0" } } } } */ \ No newline at end of file +/* { dg-final { scan-assembler-times {\mrol} 2 } } */ +/* { dg-final { scan-assembler-times {\mror} 2 } } */ +/* { dg-final { scan-assembler-not {and} { target { no-opts "-O0" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c index e7e5cbb9a1ab..f85c20eb74ad 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c @@ -14,7 +14,7 @@ unsigned int ror(unsigned int rs1, unsigned int rs2) return (rs1 >> shamt) | (rs1 << ((32 - shamt) & (32 - 1))); } -/* { dg-final { scan-assembler-times "rolw" 1 } } */ -/* { dg-final { scan-assembler-times "rorw" 1 } } */ -/* { dg-final { scan-assembler-not "and" } } */ -/* { dg-final { scan-assembler-not "sext.w" } } */ +/* { dg-final { scan-assembler-times {\mrolw} 1 } } */ +/* { dg-final { scan-assembler-times {\mrorw} 1 } } */ +/* { dg-final { scan-assembler-not {\mand} } } */ +/* { dg-final { scan-assembler-not {\msext\.w\M} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c index 7ef4c29dd5b5..28350e5e9371 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c @@ -2,7 +2,7 @@ /* { dg-options "-march=rv64gc_zbb -mabi=lp64d -fno-lto -O2" } */ /* { dg-skip-if "" { *-*-* } { "-g" } } */ /* { dg-final { check-function-bodies "**" "" } } */ -/* { dg-final { scan-assembler-not "and" } } */ +/* { dg-final { scan-assembler-not {\mand} } } */ /* **foo1: diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-05.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-05.c index 2108ccc3e779..cc44653acfbd 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-05.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-05.c @@ -2,7 +2,7 @@ /* { dg-options "-march=rv32gc_zbb -mabi=ilp32 -fno-lto -O2" } */ /* { dg-skip-if "" { *-*-* } { "-g" } } */ /* { dg-final { check-function-bodies "**" "" } } */ -/* { dg-final { scan-assembler-not "and" } } */ +/* { dg-final { scan-assembler-not {\mand} } } */ /* **foo1: diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-06.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-06.c index 8c0711d6f948..7a98a5712bfe 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-06.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-06.c @@ -2,7 +2,7 @@ /* { dg-options "-march=rv64gc_zbb -mabi=lp64d -fno-lto -O2" } */ /* { dg-skip-if "" { *-*-* } { "-g" } } */ /* { dg-final { check-function-bodies "**" "" } } */ -/* { dg-final { scan-assembler-not "and" } } */ +/* { dg-final { scan-assembler-not {\mand} } } */ /* **foo1: @@ -34,4 +34,4 @@ unsigned int foo3 (unsigned int rs1) ** ret */ unsigned int foo4 (unsigned int rs1) -{ return ((rs1 << 18) | (rs1 >> 14)); } \ No newline at end of file +{ return ((rs1 << 18) | (rs1 >> 14)); } diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-07.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-07.c index bda3f0e474d5..a08a9eb772e2 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-07.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-07.c @@ -2,7 +2,7 @@ /* { dg-options "-march=rv64gc_zbb -mabi=lp64d -fno-lto -O2" } */ /* { dg-skip-if "" { *-*-* } { "-g" } } */ /* { dg-final { check-function-bodies "**" "" } } */ -/* { dg-final { scan-assembler-not "and" } } */ +/* { dg-final { scan-assembler-not {\mand} } } */ /* **foo1: @@ -62,4 +62,4 @@ unsigned long foo4 (unsigned long rs1) tempt = tempt << 6; rs1 = tempt | (rs1 >> 20); return rs1 ; -} \ No newline at end of file +} diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-08.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-08.c index 30696f3bb32f..bf19b76b431d 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-08.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-08.c @@ -2,7 +2,7 @@ /* { dg-options "-march=rv64gc_zbb -mabi=lp64d -fno-lto -O2" } */ /* { dg-skip-if "" { *-*-* } { "-g" } } */ /* { dg-final { check-function-bodies "**" "" } } */ -/* { dg-final { scan-assembler-not "and" } } */ +/* { dg-final { scan-assembler-not {\mand} } } */ /* **foo1: diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-09.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-09.c index a3054553e184..5c4b9f58de13 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-09.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-09.c @@ -2,7 +2,7 @@ /* { dg-options "-march=rv32gc_zbb -mabi=ilp32 -fno-lto -O2" } */ /* { dg-skip-if "" { *-*-* } { "-g" } } */ /* { dg-final { check-function-bodies "**" "" } } */ -/* { dg-final { scan-assembler-not "and" } } */ +/* { dg-final { scan-assembler-not {\mand} } } */ /* **foo1: diff --git a/gcc/testsuite/gcc.target/riscv/zbb-strlen.c b/gcc/testsuite/gcc.target/riscv/zbb-strlen.c index 19ebfaef16f6..267ee414a443 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-strlen.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-strlen.c @@ -13,7 +13,7 @@ my_str_len (const char *s) } /* { dg-final { scan-assembler "orc.b\t" } } */ -/* { dg-final { scan-assembler-not "jalr" } } */ -/* { dg-final { scan-assembler-not "call" } } */ -/* { dg-final { scan-assembler-not "jr" } } */ -/* { dg-final { scan-assembler-not "tail" } } */ +/* { dg-final { scan-assembler-not {\mjalr} } } */ +/* { dg-final { scan-assembler-not {\mcall} } } */ +/* { dg-final { scan-assembler-not {\mjr} } } */ +/* { dg-final { scan-assembler-not {\mtail} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbb_32_bswap-1.c b/gcc/testsuite/gcc.target/riscv/zbb_32_bswap-1.c index 3ff7d9de4095..789dda17f05c 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb_32_bswap-1.c +++ b/gcc/testsuite/gcc.target/riscv/zbb_32_bswap-1.c @@ -7,5 +7,5 @@ int foo(int n) return __builtin_bswap32(n); } -/* { dg-final { scan-assembler "rev8" } } */ +/* { dg-final { scan-assembler {\mrev8} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbb_32_bswap-2.c b/gcc/testsuite/gcc.target/riscv/zbb_32_bswap-2.c index 679b34c4e411..3b8462d7feba 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb_32_bswap-2.c +++ b/gcc/testsuite/gcc.target/riscv/zbb_32_bswap-2.c @@ -7,6 +7,6 @@ int foo(int n) return __builtin_bswap16(n); } -/* { dg-final { scan-assembler "rev8" } } */ -/* { dg-final { scan-assembler "srli" } } */ +/* { dg-final { scan-assembler {\mrev8} } } */ +/* { dg-final { scan-assembler {\msrli} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbb_bswap-1.c b/gcc/testsuite/gcc.target/riscv/zbb_bswap-1.c index 20feded0df2e..158d97bc6e64 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb_bswap-1.c +++ b/gcc/testsuite/gcc.target/riscv/zbb_bswap-1.c @@ -7,5 +7,5 @@ int foo(int n) return __builtin_bswap32(n); } -/* { dg-final { scan-assembler "rev8" } } */ +/* { dg-final { scan-assembler {\mrev8} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbb_bswap-2.c b/gcc/testsuite/gcc.target/riscv/zbb_bswap-2.c index c358f6683f33..cb81f981ee38 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb_bswap-2.c +++ b/gcc/testsuite/gcc.target/riscv/zbb_bswap-2.c @@ -7,6 +7,6 @@ int foo(int n) return __builtin_bswap16(n); } -/* { dg-final { scan-assembler "rev8" } } */ -/* { dg-final { scan-assembler "srli" } } */ +/* { dg-final { scan-assembler {\mrev8} } } */ +/* { dg-final { scan-assembler {\msrli} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbbw.c b/gcc/testsuite/gcc.target/riscv/zbbw.c index f7b2b63853f4..bdf6b0c4ec56 100644 --- a/gcc/testsuite/gcc.target/riscv/zbbw.c +++ b/gcc/testsuite/gcc.target/riscv/zbbw.c @@ -20,7 +20,7 @@ popcount (int i) } -/* { dg-final { scan-assembler-times "clzw" 1 } } */ -/* { dg-final { scan-assembler-times "ctzw" 1 } } */ -/* { dg-final { scan-assembler-times "cpopw" 1 } } */ +/* { dg-final { scan-assembler-times {\mclzw} 1 } } */ +/* { dg-final { scan-assembler-times {\mctzw} 1 } } */ +/* { dg-final { scan-assembler-times {\mcpopw} 1 } } */ /* { dg-final { scan-assembler-not "andi\t" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbc32.c b/gcc/testsuite/gcc.target/riscv/zbc32.c index f3fb2238f7f4..049ea95c56b3 100644 --- a/gcc/testsuite/gcc.target/riscv/zbc32.c +++ b/gcc/testsuite/gcc.target/riscv/zbc32.c @@ -19,5 +19,5 @@ uint32_t foo3(uint32_t rs1, uint32_t rs2) } /* { dg-final { scan-assembler-times "clmul\t" 1 } } */ -/* { dg-final { scan-assembler-times "clmulh" 1 } } */ -/* { dg-final { scan-assembler-times "clmulr" 1 } } */ +/* { dg-final { scan-assembler-times {\mclmulh} 1 } } */ +/* { dg-final { scan-assembler-times {\mclmulr} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbc64.c b/gcc/testsuite/gcc.target/riscv/zbc64.c index 841a0aa7847d..69dadd1ca88a 100644 --- a/gcc/testsuite/gcc.target/riscv/zbc64.c +++ b/gcc/testsuite/gcc.target/riscv/zbc64.c @@ -19,5 +19,5 @@ uint64_t foo3(uint64_t rs1, uint64_t rs2) } /* { dg-final { scan-assembler-times "clmul\t" 1 } } */ -/* { dg-final { scan-assembler-times "clmulh" 1 } } */ -/* { dg-final { scan-assembler-times "clmulr" 1 } } */ +/* { dg-final { scan-assembler-times {\mclmulh} 1 } } */ +/* { dg-final { scan-assembler-times {\mclmulr} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbkb32.c b/gcc/testsuite/gcc.target/riscv/zbkb32.c index b2e442dc49d8..841f5e0d8e32 100644 --- a/gcc/testsuite/gcc.target/riscv/zbkb32.c +++ b/gcc/testsuite/gcc.target/riscv/zbkb32.c @@ -30,7 +30,7 @@ uint32_t foo5(uint32_t rs1) } /* { dg-final { scan-assembler-times "pack\t" 1 } } */ -/* { dg-final { scan-assembler-times "packh" 1 } } */ -/* { dg-final { scan-assembler-times "brev8" 1 } } */ +/* { dg-final { scan-assembler-times {\mpackh} 1 } } */ +/* { dg-final { scan-assembler-times {\mbrev8} 1 } } */ /* { dg-final { scan-assembler-times "\tzip\t" 1 } } */ -/* { dg-final { scan-assembler-times "unzip" 1 } } */ +/* { dg-final { scan-assembler-times {\munzip} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbkb64.c b/gcc/testsuite/gcc.target/riscv/zbkb64.c index 08ac9c2a9f00..8b6a0bff1f2d 100644 --- a/gcc/testsuite/gcc.target/riscv/zbkb64.c +++ b/gcc/testsuite/gcc.target/riscv/zbkb64.c @@ -23,6 +23,6 @@ uint64_t foo4(uint64_t rs1, uint64_t rs2) return __builtin_riscv_brev8(rs1); } /* { dg-final { scan-assembler-times "pack\t" 1 } } */ -/* { dg-final { scan-assembler-times "packh" 1 } } */ -/* { dg-final { scan-assembler-times "packw" 1 } } */ -/* { dg-final { scan-assembler-times "brev8" 1 } } */ +/* { dg-final { scan-assembler-times {\mpackh} 1 } } */ +/* { dg-final { scan-assembler-times {\mpackw} 1 } } */ +/* { dg-final { scan-assembler-times {\mbrev8} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbkc32.c b/gcc/testsuite/gcc.target/riscv/zbkc32.c index 29f0d624a7d7..6d2a8fffbc1a 100644 --- a/gcc/testsuite/gcc.target/riscv/zbkc32.c +++ b/gcc/testsuite/gcc.target/riscv/zbkc32.c @@ -14,4 +14,4 @@ uint32_t foo2(uint32_t rs1, uint32_t rs2) } /* { dg-final { scan-assembler-times "clmul\t" 1 } } */ -/* { dg-final { scan-assembler-times "clmulh" 1 } } */ +/* { dg-final { scan-assembler-times {\mclmulh} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbkc64.c b/gcc/testsuite/gcc.target/riscv/zbkc64.c index 53e6ac215ed3..3708fb5fbb11 100644 --- a/gcc/testsuite/gcc.target/riscv/zbkc64.c +++ b/gcc/testsuite/gcc.target/riscv/zbkc64.c @@ -14,4 +14,4 @@ uint64_t foo2(uint64_t rs1, uint64_t rs2) } /* { dg-final { scan-assembler-times "clmul\t" 1 } } */ -/* { dg-final { scan-assembler-times "clmulh" 1 } } */ +/* { dg-final { scan-assembler-times {\mclmulh} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbkx32.c b/gcc/testsuite/gcc.target/riscv/zbkx32.c index b8b822a7c499..b41fd90de519 100644 --- a/gcc/testsuite/gcc.target/riscv/zbkx32.c +++ b/gcc/testsuite/gcc.target/riscv/zbkx32.c @@ -14,5 +14,5 @@ uint32_t foo4(uint32_t rs1, uint32_t rs2) return __builtin_riscv_xperm4(rs1, rs2); } -/* { dg-final { scan-assembler-times "xperm8" 1 } } */ -/* { dg-final { scan-assembler-times "xperm4" 1 } } */ +/* { dg-final { scan-assembler-times {\mxperm8} 1 } } */ +/* { dg-final { scan-assembler-times {\mxperm4} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbkx64.c b/gcc/testsuite/gcc.target/riscv/zbkx64.c index 732436701b33..9ed42b407186 100644 --- a/gcc/testsuite/gcc.target/riscv/zbkx64.c +++ b/gcc/testsuite/gcc.target/riscv/zbkx64.c @@ -14,5 +14,5 @@ uint64_t foo2(uint64_t rs1, uint64_t rs2) return __builtin_riscv_xperm4(rs1, rs2); } -/* { dg-final { scan-assembler-times "xperm8" 1 } } */ -/* { dg-final { scan-assembler-times "xperm4" 1 } } */ +/* { dg-final { scan-assembler-times {\mxperm8} 1 } } */ +/* { dg-final { scan-assembler-times {\mxperm4} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bclr.c b/gcc/testsuite/gcc.target/riscv/zbs-bclr.c index 5d7daa3b8260..e37580dc245f 100644 --- a/gcc/testsuite/gcc.target/riscv/zbs-bclr.c +++ b/gcc/testsuite/gcc.target/riscv/zbs-bclr.c @@ -18,4 +18,4 @@ foo1 (long i) /* { dg-final { scan-assembler-times "bclr\t" 1 } } */ /* { dg-final { scan-assembler-times "bclri\t" 1 } } */ -/* { dg-final { scan-assembler-not "andi" } } */ +/* { dg-final { scan-assembler-not {\mandi} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bext-02.c b/gcc/testsuite/gcc.target/riscv/zbs-bext-02.c index 3f3b8404eca5..8c5d8c7a41a7 100644 --- a/gcc/testsuite/gcc.target/riscv/zbs-bext-02.c +++ b/gcc/testsuite/gcc.target/riscv/zbs-bext-02.c @@ -14,5 +14,5 @@ foo(const long long B, int a) } /* { dg-final { scan-assembler-times "bext\t" 1 } } */ -/* { dg-final { scan-assembler-not "bset" } } */ -/* { dg-final { scan-assembler-not "and" } } */ +/* { dg-final { scan-assembler-not {\mbset} } } */ +/* { dg-final { scan-assembler-not {\mand} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bext.c b/gcc/testsuite/gcc.target/riscv/zbs-bext.c index a8aadb603909..ff75dad65285 100644 --- a/gcc/testsuite/gcc.target/riscv/zbs-bext.c +++ b/gcc/testsuite/gcc.target/riscv/zbs-bext.c @@ -41,4 +41,4 @@ long bext64_4(long a, char bitno) /* { dg-final { scan-assembler-times "xori\t|snez\t" 1 } } */ /* { dg-final { scan-assembler-times "addi\t" 1 } } */ /* { dg-final { scan-assembler-times "neg\t" 1 } } */ -/* { dg-final { scan-assembler-not "andi" } } */ \ No newline at end of file +/* { dg-final { scan-assembler-not {\mandi} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbs-binv.c b/gcc/testsuite/gcc.target/riscv/zbs-binv.c index d8d6e47f4356..f4bf27e9071f 100644 --- a/gcc/testsuite/gcc.target/riscv/zbs-binv.c +++ b/gcc/testsuite/gcc.target/riscv/zbs-binv.c @@ -18,4 +18,4 @@ foo1 (long i) /* { dg-final { scan-assembler-times "binv\t" 1 } } */ /* { dg-final { scan-assembler-times "binvi\t" 1 } } */ -/* { dg-final { scan-assembler-not "andi" } } */ +/* { dg-final { scan-assembler-not {\mandi} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bset.c b/gcc/testsuite/gcc.target/riscv/zbs-bset.c index cea2b64bafcf..4a5b6f5cb578 100644 --- a/gcc/testsuite/gcc.target/riscv/zbs-bset.c +++ b/gcc/testsuite/gcc.target/riscv/zbs-bset.c @@ -39,4 +39,4 @@ sub4 (long i) /* { dg-final { scan-assembler-times "bset\t" 4 } } */ /* { dg-final { scan-assembler-times "bseti\t" 1 } } */ -/* { dg-final { scan-assembler-not "andi" } } */ +/* { dg-final { scan-assembler-not {\mandi} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zero-extend-1.c b/gcc/testsuite/gcc.target/riscv/zero-extend-1.c index b61ea8eff6b3..754842feddde 100644 --- a/gcc/testsuite/gcc.target/riscv/zero-extend-1.c +++ b/gcc/testsuite/gcc.target/riscv/zero-extend-1.c @@ -5,4 +5,4 @@ sub1 (unsigned int i) { return i >> 1; } -/* { dg-final { scan-assembler-times "srliw" 1 } } */ +/* { dg-final { scan-assembler-times {\msrliw} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zero-extend-2.c b/gcc/testsuite/gcc.target/riscv/zero-extend-2.c index c3d6eeb1f7d0..da48fe574632 100644 --- a/gcc/testsuite/gcc.target/riscv/zero-extend-2.c +++ b/gcc/testsuite/gcc.target/riscv/zero-extend-2.c @@ -10,4 +10,4 @@ sub (unsigned int wc, unsigned long step, unsigned char *start) } while (step > 1); } -/* { dg-final { scan-assembler-times "sext.w" 0 } } */ +/* { dg-final { scan-assembler-times {\msext\.w\M} 0 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zero-extend-3.c b/gcc/testsuite/gcc.target/riscv/zero-extend-3.c index 6485ebd59344..c567300f4acc 100644 --- a/gcc/testsuite/gcc.target/riscv/zero-extend-3.c +++ b/gcc/testsuite/gcc.target/riscv/zero-extend-3.c @@ -9,4 +9,4 @@ c (void) d = b; return d; } -/* { dg-final { scan-assembler-times "sext.w" 0 } } */ +/* { dg-final { scan-assembler-times {\msext\.w\M} 0 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zero-extend-4.c b/gcc/testsuite/gcc.target/riscv/zero-extend-4.c index e1a8922bb286..3c776b09d6e4 100644 --- a/gcc/testsuite/gcc.target/riscv/zero-extend-4.c +++ b/gcc/testsuite/gcc.target/riscv/zero-extend-4.c @@ -18,4 +18,4 @@ f(void) d->binmap[0] = e; } } -/* { dg-final { scan-assembler-times "sext.w" 0 } } */ +/* { dg-final { scan-assembler-times {\msext\.w\M} 0 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zero-extend-5.c b/gcc/testsuite/gcc.target/riscv/zero-extend-5.c index 4e58a151f628..2f689614dcef 100644 --- a/gcc/testsuite/gcc.target/riscv/zero-extend-5.c +++ b/gcc/testsuite/gcc.target/riscv/zero-extend-5.c @@ -5,4 +5,4 @@ sub (unsigned int i, unsigned int j, unsigned int k, int *array) { return array[i] + array[j] + array[k]; } -/* { dg-final { scan-assembler-times "slli" 3 } } */ +/* { dg-final { scan-assembler-times {\mslli} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c index 9161dd3d4ec8..cf3dfac1949b 100644 --- a/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c +++ b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c @@ -6,7 +6,7 @@ foo (void) { } -/* { dg-final { scan-assembler-not "vsetvli" } } */ +/* { dg-final { scan-assembler-not {\mvsetvli} } } */ /* { dg-final { scan-assembler "li\[ \t\]*t0,0" } } */ /* { dg-final { scan-assembler "li\[ \t\]*t1,0" } } */ /* { dg-final { scan-assembler "li\[ \t\]*t2,0" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zfa-fleq-fltq.c b/gcc/testsuite/gcc.target/riscv/zfa-fleq-fltq.c index 7c28b0bcccc7..74777387f406 100644 --- a/gcc/testsuite/gcc.target/riscv/zfa-fleq-fltq.c +++ b/gcc/testsuite/gcc.target/riscv/zfa-fleq-fltq.c @@ -14,7 +14,7 @@ foo() abort(); } -/* { dg-final { scan-assembler-times "fleq.s" 1 } } */ -/* { dg-final { scan-assembler-times "fltq.s" 1 } } */ -/* { dg-final { scan-assembler-times "fleq.d" 1 } } */ -/* { dg-final { scan-assembler-times "fltq.d" 1 } } */ +/* { dg-final { scan-assembler-times {\mfleq\.s\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mfltq\.s\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mfleq\.d\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mfltq\.d\M} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zfa-fli-zfh.c b/gcc/testsuite/gcc.target/riscv/zfa-fli-zfh.c index 05e2dcbe45eb..a97c7bd250f9 100644 --- a/gcc/testsuite/gcc.target/riscv/zfa-fli-zfh.c +++ b/gcc/testsuite/gcc.target/riscv/zfa-fli-zfh.c @@ -39,4 +39,4 @@ void foo_float16 () a = __builtin_nanf16 (""); } -/* { dg-final { scan-assembler-times "fli.h" 32 } } */ +/* { dg-final { scan-assembler-times {\mfli\.h\M} 32 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zfa-fli.c b/gcc/testsuite/gcc.target/riscv/zfa-fli.c index e5c1e591c8c8..d7269c5f68a1 100644 --- a/gcc/testsuite/gcc.target/riscv/zfa-fli.c +++ b/gcc/testsuite/gcc.target/riscv/zfa-fli.c @@ -76,5 +76,5 @@ void foo_double64 () a = __builtin_nan (""); } -/* { dg-final { scan-assembler-times "fli.s" 32 } } */ -/* { dg-final { scan-assembler-times "fli.d" 32 } } */ +/* { dg-final { scan-assembler-times {\mfli\.s\M} 32 } } */ +/* { dg-final { scan-assembler-times {\mfli\.d\M} 32 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics.c b/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics.c index 47d4e4c5683a..bcfa04bef91e 100644 --- a/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics.c +++ b/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics.c @@ -43,7 +43,7 @@ int primitiveSemantics_11(int a, int b) { return b; } -/* { dg-final { scan-assembler-times "czero.eqz" 6 } } */ -/* { dg-final { scan-assembler-times "czero.nez" 6 } } */ -/* { dg-final { scan-assembler-not "beq" } } */ -/* { dg-final { scan-assembler-not "bne" } } */ +/* { dg-final { scan-assembler-times {\mczero\.eqz\M} 6 } } */ +/* { dg-final { scan-assembler-times {\mczero\.nez\M} 6 } } */ +/* { dg-final { scan-assembler-not {\mbeq} } } */ +/* { dg-final { scan-assembler-not {\mbne} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_0_imm.c b/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_0_imm.c index 76773d32a8bd..0764d2919d44 100644 --- a/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_0_imm.c +++ b/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_0_imm.c @@ -59,7 +59,7 @@ int primitiveSemantics_return_0_imm_11(int a, int b) { return b; } -/* { dg-final { scan-assembler-times "czero.eqz" 6 } } */ -/* { dg-final { scan-assembler-times "czero.nez" 6 } } */ -/* { dg-final { scan-assembler-not "beq" } } */ -/* { dg-final { scan-assembler-not "bne" } } */ +/* { dg-final { scan-assembler-times {\mczero\.eqz\M} 6 } } */ +/* { dg-final { scan-assembler-times {\mczero\.nez\M} 6 } } */ +/* { dg-final { scan-assembler-not {\mbeq} } } */ +/* { dg-final { scan-assembler-not {\mbne} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_imm_imm.c b/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_imm_imm.c index 2b4ee956eb71..2ff5033bb040 100644 --- a/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_imm_imm.c +++ b/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_imm_imm.c @@ -67,7 +67,7 @@ int primitiveSemantics_return_imm_imm_11(int a, int b) { return b; } -/* { dg-final { scan-assembler-times "czero.eqz" 6 } } */ -/* { dg-final { scan-assembler-times "czero.nez" 6 } } */ -/* { dg-final { scan-assembler-not "beq" } } */ -/* { dg-final { scan-assembler-not "bne" } } */ +/* { dg-final { scan-assembler-times {\mczero\.eqz\M} 6 } } */ +/* { dg-final { scan-assembler-times {\mczero\.nez\M} 6 } } */ +/* { dg-final { scan-assembler-not {\mbeq} } } */ +/* { dg-final { scan-assembler-not {\mbne} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_imm_reg.c b/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_imm_reg.c index 4a96560eb61e..93844d166c35 100644 --- a/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_imm_reg.c +++ b/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_imm_reg.c @@ -59,7 +59,7 @@ int primitiveSemantics_return_imm_reg_11(int a, int b) { return b; } -/* { dg-final { scan-assembler-times "czero.eqz" 6 } } */ -/* { dg-final { scan-assembler-times "czero.nez" 6 } } */ -/* { dg-final { scan-assembler-not "beq" } } */ -/* { dg-final { scan-assembler-not "bne" } } */ +/* { dg-final { scan-assembler-times {\mczero\.eqz\M} 6 } } */ +/* { dg-final { scan-assembler-times {\mczero\.nez\M} 6 } } */ +/* { dg-final { scan-assembler-not {\mbeq} } } */ +/* { dg-final { scan-assembler-not {\mbne} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_reg_reg.c b/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_reg_reg.c index 0624b6f16d47..619ad8ecf7d2 100644 --- a/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_reg_reg.c +++ b/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_reg_reg.c @@ -59,7 +59,7 @@ int primitiveSemantics_return_reg_reg_11(int a, int b, int c) { return b; } -/* { dg-final { scan-assembler-times "czero.eqz" 12 } } */ -/* { dg-final { scan-assembler-times "czero.nez" 12 } } */ -/* { dg-final { scan-assembler-not "beq" } } */ -/* { dg-final { scan-assembler-not "bne" } } */ +/* { dg-final { scan-assembler-times {\mczero\.eqz\M} 12 } } */ +/* { dg-final { scan-assembler-times {\mczero\.nez\M} 12 } } */ +/* { dg-final { scan-assembler-not {\mbeq} } } */ +/* { dg-final { scan-assembler-not {\mbne} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zknd64.c b/gcc/testsuite/gcc.target/riscv/zknd64.c index 910b91c6ed88..707418cd51e7 100644 --- a/gcc/testsuite/gcc.target/riscv/zknd64.c +++ b/gcc/testsuite/gcc.target/riscv/zknd64.c @@ -33,4 +33,4 @@ uint64_t foo5(uint64_t rs1) /* { dg-final { scan-assembler-times "aes64dsm" 1 } } */ /* { dg-final { scan-assembler-times "aes64ks1i" 1 } } */ /* { dg-final { scan-assembler-times "aes64ks2" 1 } } */ -/* { dg-final { scan-assembler-times "aes64im" 1 } } */ +/* { dg-final { scan-assembler-times {\maes64im} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zksed32.c b/gcc/testsuite/gcc.target/riscv/zksed32.c index 7df04147e05c..0e8f01cd5485 100644 --- a/gcc/testsuite/gcc.target/riscv/zksed32.c +++ b/gcc/testsuite/gcc.target/riscv/zksed32.c @@ -15,5 +15,5 @@ uint32_t foo2(uint32_t rs1, uint32_t rs2, unsigned bs) } -/* { dg-final { scan-assembler-times "sm4ks" 1 } } */ -/* { dg-final { scan-assembler-times "sm4ed" 1 } } */ +/* { dg-final { scan-assembler-times {\msm4ks} 1 } } */ +/* { dg-final { scan-assembler-times {\msm4ed} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zksed64.c b/gcc/testsuite/gcc.target/riscv/zksed64.c index 913e7be4e4d9..9e4d1961419c 100644 --- a/gcc/testsuite/gcc.target/riscv/zksed64.c +++ b/gcc/testsuite/gcc.target/riscv/zksed64.c @@ -15,5 +15,5 @@ uint32_t foo2(uint32_t rs1, uint32_t rs2, unsigned bs) } -/* { dg-final { scan-assembler-times "sm4ks" 1 } } */ -/* { dg-final { scan-assembler-times "sm4ed" 1 } } */ +/* { dg-final { scan-assembler-times {\msm4ks} 1 } } */ +/* { dg-final { scan-assembler-times {\msm4ed} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zksh32.c b/gcc/testsuite/gcc.target/riscv/zksh32.c index 20513f986f88..c182e557a858 100644 --- a/gcc/testsuite/gcc.target/riscv/zksh32.c +++ b/gcc/testsuite/gcc.target/riscv/zksh32.c @@ -15,5 +15,5 @@ uint32_t foo2(uint32_t rs1) } -/* { dg-final { scan-assembler-times "sm3p0" 1 } } */ -/* { dg-final { scan-assembler-times "sm3p1" 1 } } */ +/* { dg-final { scan-assembler-times {\msm3p0} 1 } } */ +/* { dg-final { scan-assembler-times {\msm3p1} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zksh64.c b/gcc/testsuite/gcc.target/riscv/zksh64.c index 30bb1bdeeeb7..d794b39f77af 100644 --- a/gcc/testsuite/gcc.target/riscv/zksh64.c +++ b/gcc/testsuite/gcc.target/riscv/zksh64.c @@ -15,5 +15,5 @@ uint32_t foo2(uint32_t rs1) } -/* { dg-final { scan-assembler-times "sm3p0" 1 } } */ -/* { dg-final { scan-assembler-times "sm3p1" 1 } } */ +/* { dg-final { scan-assembler-times {\msm3p0} 1 } } */ +/* { dg-final { scan-assembler-times {\msm3p1} 1 } } */