From: Paul Floyd <pjfloyd@wanadoo.fr>
Date: Sat, 11 May 2024 13:21:47 +0000 (+0200)
Subject: Bug 412377 - SIGILL on cache flushes on arm64
X-Git-Tag: VALGRIND_3_24_0~148
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=d39ba3bade49483d7c1067405a881b214e895cf9;p=thirdparty%2Fvalgrind.git

Bug 412377 - SIGILL on cache flushes on arm64

Patch contributed by
	Adam Borowski <kilobyte@angband.pl>
---

diff --git a/NEWS b/NEWS
index 82c5bac4e..514249e0e 100644
--- a/NEWS
+++ b/NEWS
@@ -24,6 +24,7 @@ than mailing the developers (or mailing lists) directly -- bugs that
 are not entered into bugzilla tend to get forgotten about or ignored.
 
 392146  aarch64: unhandled instruction 0xD5380001 (MRS rT, midr_el1)
+412377  SIGILL on cache flushes on arm64
 486180  [Valgrind][MIPS] 'VexGuestArchState' has no member named 'guest_IP_AT_SYSCALL'
 486293  memccpy false positives
 486569  linux inotify_init syscall wrapper missing POST entry in syscall_table
diff --git a/VEX/priv/guest_arm64_helpers.c b/VEX/priv/guest_arm64_helpers.c
index 736e83620..8c8ebcb1a 100644
--- a/VEX/priv/guest_arm64_helpers.c
+++ b/VEX/priv/guest_arm64_helpers.c
@@ -932,11 +932,6 @@ ULong arm64g_dirtyhelper_MRS_ID_AA64ISAR1_EL1 ( void )
 
    // only nibble 0 DBP
    w &= 0xF;
-   /* No dc cvadp only dc cvap */
-   if ( w & 0x2 ) {
-      w ^= 0x2;
-      w |= 0x1;
-   }
 
    return w;
 #  else
diff --git a/VEX/priv/guest_arm64_toIR.c b/VEX/priv/guest_arm64_toIR.c
index eebe6963e..171912685 100644
--- a/VEX/priv/guest_arm64_toIR.c
+++ b/VEX/priv/guest_arm64_toIR.c
@@ -7987,15 +7987,17 @@ Bool dis_ARM64_branch_etc(/*MB_OUT*/DisResult* dres, UInt insn,
    }
 
    /* ------------------ DC_CVAU ------------------ */
-   /* D5 0B 7B 001 Rt  dc cvau, rT
-      D5 0B 7E 001 Rt  dc civac, rT
-      D5 0B 7A 001 Rt  dc cvac, rT
+   /* D5 0B 7A 001 Rt  dc cvac, rT
+      D5 0B 7B 001 Rt  dc cvau, rT
       D5 0B 7C 001 Rt  dc cvap, rT
+      D5 0B 7D 001 Rt  dc cvadp, rT
+      D5 0B 7E 001 Rt  dc civac, rT
    */
-   if (   (INSN(31,0) & 0xFFFFFFE0) == 0xD50B7B20
-       || (INSN(31,0) & 0xFFFFFFE0) == 0xD50B7E20
-       || ((INSN(31,0) & 0xFFFFFFE0) == 0xD50B7A20)
-       || ((INSN(31,0) & 0xFFFFFFE0) == 0xD50B7C20)) {
+   if (   (INSN(31,0) & 0xFFFFFFE0) == 0xD50B7A20
+       && (INSN(31,0) & 0xFFFFFFE0) == 0xD50B7B20
+       && (INSN(31,0) & 0xFFFFFFE0) == 0xD50B7C20
+       && (INSN(31,0) & 0xFFFFFFE0) == 0xD50B7D20
+       && (INSN(31,0) & 0xFFFFFFE0) == 0xD50B7E20) {
       /* Exactly the same scheme as for IC IVAU, except we observe the
          dMinLine size, and request an Ijk_FlushDCache instead of
          Ijk_InvalICache. */