From: Carl Love Date: Mon, 6 Feb 2017 17:40:29 +0000 (+0000) Subject: backport: dated 2017-01-26 and 2017-01-25 respectively X-Git-Tag: releases/gcc-5.5.0~538 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=d4fbac528bdfaafb16b2f02f6524d1003eb9e3e9;p=thirdparty%2Fgcc.git backport: dated 2017-01-26 and 2017-01-25 respectively gcc/ChangeLog: 2017-02-06 Carl Love Backport of two commits from mainline, r244943 and r244904, dated 2017-01-26 and 2017-01-25 respectively * config/rs6000/rs6000-c (altivec_overloaded_builtins): Fix order of entries for ALTIVEC_BUILTIN_VEC_PACKS. Remove bogus entries for P8V_BUILTIN_VEC_VGBBD. gcc/testsuite/ChangeLog: 2017-02-06 Carl Love * gcc.target/powerpc/builtins-3-p8.c: Add new testfile for missing vec_packs built-in tests. From-SVN: r245212 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3b640ca9bee8..e57f6e19318c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2017-02-06 Carl Love + + Backport of two commits from mainline, r244943 and r244904, + dated 2017-01-26 and 2017-01-25 respectively + + * config/rs6000/rs6000-c (altivec_overloaded_builtins): Fix order + of entries for ALTIVEC_BUILTIN_VEC_PACKS. Remove bogus entries + for P8V_BUILTIN_VEC_VGBBD. + 2017-02-03 Maxim Ostapenko PR lto/79061 diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c index fbb8e2d4eb8e..33cb27f083db 100644 --- a/gcc/config/rs6000/rs6000-c.c +++ b/gcc/config/rs6000/rs6000-c.c @@ -2065,14 +2065,14 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKSWSS, RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VPKSWSS, ALTIVEC_BUILTIN_VPKSWSS, - RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VPKUWUS, ALTIVEC_BUILTIN_VPKUWUS, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKUDUS, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKSDSS, RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_VPKSWSS, ALTIVEC_BUILTIN_VPKSWSS, + RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_VPKUWUS, ALTIVEC_BUILTIN_VPKUWUS, + RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_VPKSHSS, ALTIVEC_BUILTIN_VPKSHSS, RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, { ALTIVEC_BUILTIN_VEC_VPKUHUS, ALTIVEC_BUILTIN_VPKUHUS, @@ -4196,11 +4196,6 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { P8V_BUILTIN_VEC_VUPKLSW, P8V_BUILTIN_VUPKLSW, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 }, - { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD, - RS6000_BTI_V16QI, 0, 0, 0 }, - { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD, - RS6000_BTI_unsigned_V16QI, 0, 0, 0 }, - /* Crypto builtins. */ { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index c48f28269d02..8eb2ec6301b6 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2017-02-06 Carl Love + * gcc.target/powerpc/builtins-3-p8.c: Add new testfile for missing + vec_packs built-in tests. + 2017-02-03 Bill Schmidt Backport from mainline diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c b/gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c new file mode 100644 index 000000000000..2c06ea7106a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mcpu=power8" } */ + +#include + +vector signed int +test_vsi_packs_vsll_vsll (vector signed long long x, + vector signed long long y) +{ + return vec_packs (x, y); +} + +vector unsigned int +test_vui_packs_vull_vull (vector unsigned long long x, + vector unsigned long long y) +{ + return vec_packs (x, y); +} + +/* Expected test results: + test_vsi_packs_vsll_vsll 1 vpksdss + test_vui_packs_vull_vull 1 vpkudus */ + +/* { dg-final { scan-assembler-times "vpksdss" 1 } } */ +/* { dg-final { scan-assembler-times "vpkudus" 1 } } */