From: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com>
Date: Mon, 17 Nov 2025 14:24:37 +0000 (+0000)
Subject: dt-bindings: cache: sifive,ccache0: add a pic64gx compatible
X-Git-Tag: v6.19-rc1~97^2~1^2~8
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=d52341da4db0cd993d3549aa20cbdf063b412c3b;p=thirdparty%2Fkernel%2Flinux.git

dt-bindings: cache: sifive,ccache0: add a pic64gx compatible

The pic64gx use the same IP than mpfs, therefore add compatibility with
mpfs as fallback.

Signed-off-by: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---

diff --git a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
index 579bacb66f348..c0e5ebb1fa4c7 100644
--- a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
+++ b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
@@ -48,6 +48,11 @@ properties:
           - const: microchip,mpfs-ccache
           - const: sifive,fu540-c000-ccache
           - const: cache
+      - items:
+          - const: microchip,pic64gx-ccache
+          - const: microchip,mpfs-ccache
+          - const: sifive,fu540-c000-ccache
+          - const: cache
 
   cache-block-size:
     const: 64