From: Dmitry Baryshkov Date: Fri, 21 Feb 2025 15:52:01 +0000 (+0200) Subject: dt-bindings: PCI: qcom-ep: Enable DMA for SM8450 X-Git-Tag: v6.15-rc1~119^2~4^2~3 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=d589fe0bf0c45f84db75535466dc2e02e304147f;p=thirdparty%2Fkernel%2Flinux.git dt-bindings: PCI: qcom-ep: Enable DMA for SM8450 Qualcomm SM8450 platform can (and should) be using DMA for the PCIe Endpoint transfers. Thus, extend the MMIO regions and interrupts in order to acommodate for the DMA resources, mark iommus property as required for the platform. Upstream devicetree doesn't provide support for the Endpoint mode of the PCIe controller, so while this is an ABI break, it doesn't break any of the supported platforms. Fixes: 63e445b746aa ("dt-bindings: PCI: qcom-ep: Add support for SM8450 SoC") Reviewed-by: Manivannan Sadhasivam Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250221-sar2130p-pci-v3-3-61a0fdfb75b4@linaro.org [kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński --- diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml index 6075361348352..d22022ff2760c 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml @@ -176,9 +176,11 @@ allOf: then: properties: reg: - maxItems: 6 + minItems: 7 + maxItems: 7 reg-names: - maxItems: 6 + minItems: 7 + maxItems: 7 clocks: items: - description: PCIe Auxiliary clock @@ -200,9 +202,13 @@ allOf: - const: ddrss_sf_tbu - const: aggre_noc_axi interrupts: - maxItems: 2 + minItems: 3 + maxItems: 3 interrupt-names: - maxItems: 2 + minItems: 3 + maxItems: 3 + required: + - iommus - if: properties: