From: Conor Dooley Date: Mon, 12 May 2025 13:48:14 +0000 (+0100) Subject: dt-bindings: cache: add specific RZ/Five compatible to ax45mp X-Git-Tag: v6.16-rc1~100^2~2^2~3 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=d58a73c96d8ae87936579689af1dd60a09bda432;p=thirdparty%2Fkernel%2Fstable.git dt-bindings: cache: add specific RZ/Five compatible to ax45mp When the binding was originally written, it was assumed that all ax45mp-caches had the same properties etc. This has turned out to be incorrect, as the QiLai SoC has a different number of cache-sets. Add a specific compatible for the RZ/Five for property enforcement and in case there turns out to be additional differences between these implementations of the cache controller. Acked-by: Ben Zong-You Xie Reviewed-by: Geert Uytterhoeven Signed-off-by: Conor Dooley --- diff --git a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml index d2cbe49f4e15f..82668d327344e 100644 --- a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml +++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml @@ -28,6 +28,7 @@ select: properties: compatible: items: + - const: renesas,r9a07g043f-ax45mp-cache - const: andestech,ax45mp-cache - const: cache @@ -70,7 +71,8 @@ examples: #include cache-controller@13400000 { - compatible = "andestech,ax45mp-cache", "cache"; + compatible = "renesas,r9a07g043f-ax45mp-cache", "andestech,ax45mp-cache", + "cache"; reg = <0x13400000 0x100000>; interrupts = <508 IRQ_TYPE_LEVEL_HIGH>; cache-line-size = <64>;