From: Vikas Gupta Date: Tue, 2 Apr 2024 09:37:47 +0000 (-0700) Subject: bnxt_en: Add delay to handle Downstream Port Containment (DPC) AER X-Git-Tag: v6.10-rc1~153^2~358^2~6 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=d5ab32e9b02dc228444add3502261ad68391bf30;p=thirdparty%2Fkernel%2Flinux.git bnxt_en: Add delay to handle Downstream Port Containment (DPC) AER In case of DPC, after issuing the hot reset, the kernel waits for 100ms for the device to complete the reset. However on some older chips, the firmware may take up to 1 second to complete the reset, only after which the driver can restart the card. Introduce delay of 900ms to handle this scenario on the older chipsets. Signed-off-by: Vikas Gupta Reviewed-by: Michael Chan Reviewed-by: Somnath Kotur Signed-off-by: Pavan Chebbi Acked-by: Paolo Abeni Link: https://lore.kernel.org/r/20240402093753.331120-2-pavan.chebbi@broadcom.com Signed-off-by: Jakub Kicinski --- diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt.c b/drivers/net/ethernet/broadcom/bnxt/bnxt.c index b4db4b1aaffbf..6e24a341ad28d 100644 --- a/drivers/net/ethernet/broadcom/bnxt/bnxt.c +++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.c @@ -15550,6 +15550,10 @@ static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev) netdev_info(bp->dev, "PCI Slot Reset\n"); + if (!(bp->flags & BNXT_FLAG_CHIP_P5_PLUS) && + test_bit(BNXT_STATE_PCI_CHANNEL_IO_FROZEN, &bp->state)) + msleep(900); + rtnl_lock(); if (pci_enable_device(pdev)) {