From: Rodrigo Siqueira Date: Wed, 19 Nov 2025 00:45:52 +0000 (-0700) Subject: Documentation/gpu: Expand generic block information X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=d68ba530ec79ec02c5432c3ae9c852081cc5ebb1;p=thirdparty%2Fkernel%2Flinux.git Documentation/gpu: Expand generic block information This commit expands the overall explanation about AMD GPU IPs by adding more details about their interconnection. Note that this commit includes a diagram that provides additional information. v2: fix up TMR - Trusted Memory Region Cc: Alex Deucher Cc: Christian König Cc: Timur Kristóf Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher --- diff --git a/Documentation/gpu/amdgpu/amd_overview_block.svg b/Documentation/gpu/amdgpu/amd_overview_block.svg new file mode 100644 index 0000000000000..cbd705afc9e2d --- /dev/null +++ b/Documentation/gpu/amdgpu/amd_overview_block.svg @@ -0,0 +1,687 @@ + + + + + + + + + + + + + + + + + + + + + + UMC + + + + Memory hub + + + + + PSP + + + + + PCIe (NBIO) + + + SMU + + + + + + + SDMA + + + + + + + + + + Reset + + + + + PSP Interaction + + + + + + + + + + + + + + Firmware + + + + Memory + Memory + Memory + Memory + + + + UMC + + + UMC + + + Graphics & Compute (GC) + + ShaderEngine(SE)#1 + + + + SE #2 + + + + SE #N + + + ... + + + + + VCN + + + + DCN + + + diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst b/Documentation/gpu/amdgpu/amdgpu-glossary.rst index ac13213d84faf..033167025fcca 100644 --- a/Documentation/gpu/amdgpu/amdgpu-glossary.rst +++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst @@ -240,9 +240,18 @@ we have a dedicated glossary for Display Core at stages had different cache designs; it refers to the L1 cache in older architectures. + TMR + Trusted Memory Region + + TMZ + Trusted Memory Zone + TOC Table of Contents + UMC + Unified Memory Controller + UMSCH User Mode Scheduler diff --git a/Documentation/gpu/amdgpu/display/dc-glossary.rst b/Documentation/gpu/amdgpu/display/dc-glossary.rst index cbe737d1fcead..accb7c05308c5 100644 --- a/Documentation/gpu/amdgpu/display/dc-glossary.rst +++ b/Documentation/gpu/amdgpu/display/dc-glossary.rst @@ -221,9 +221,6 @@ consider asking on the amd-gfx mailing list and update this page. TMDS Transition-Minimized Differential Signaling - TMZ - Trusted Memory Zone - TTU Time to Underflow diff --git a/Documentation/gpu/amdgpu/driver-core.rst b/Documentation/gpu/amdgpu/driver-core.rst index 3ce276272171e..2c2bbf7caf1a0 100644 --- a/Documentation/gpu/amdgpu/driver-core.rst +++ b/Documentation/gpu/amdgpu/driver-core.rst @@ -77,6 +77,37 @@ VCN (Video Core Next) decode. It's exposed to userspace for user mode drivers (VA-API, OpenMAX, etc.) +It is important to note that these blocks can interact with each other. The +picture below illustrates some of the components and their interconnection: + +.. kernel-figure:: amd_overview_block.svg + +In the diagram, memory-related blocks are shown in green. Notice that specific +IPs have a green square that represents a small hardware block named 'hub', +which is responsible for interfacing with memory. All memory hubs are connected +in the UMCs, which in turn are connected to memory blocks. As a note, +pre-vega devices have a dedicated block for the Graphic Memory Controller +(GMC), which was replaced by UMC and hubs in new architectures. In the driver +code, you can identify this component by looking for the suffix hub, for +example: gfxhub, dchub, mmhub, vmhub, etc. Keep in mind that the component's +interaction with the memory block may vary across architectures. For example, +on Navi and newer, GC and SDMA are both attached to GCHUB; on pre-Navi, SDMA +goes through MMHUB; VCN, JPEG, and VPE go through MMHUB; DCN goes through +DCHUB. + +There is some protection for certain memory elements, and the PSP plays an +essential role in this area. When a specific firmware is loaded into memory, +the PSP takes steps to ensure it has a valid signature. It also stores firmware +images in a protected memory area named Trusted Memory Area (TMR), so the OS or +driver can't corrupt them at runtime. Another use of PSP is to support Trusted +Applications (TA), which are basically small applications that run on the +trusted processor and handles a trusted operation (e.g., HDCP). PSP is also +used for encrypted memory for content protection via Trusted Memory Zone (TMZ). + +Another critical IP is the SMU. It handles reset distribution, as well as +clock, thermal, and power management for all IPs on the SoC. SMU also helps to +balance performance and power consumption. + .. _pipes-and-queues-description: GFX, Compute, and SDMA Overall Behavior