From: Alan Modra <amodra@gmail.com>
Date: Mon, 26 Oct 2020 11:21:31 +0000 (+1030)
Subject: [RS6000] Replace -mcpu with -mdejagnu-cpu
X-Git-Tag: basepoints/gcc-12~3858
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=d7c71335c2a5bd65ee36b927af83ef97a1e06620;p=thirdparty%2Fgcc.git

[RS6000] Replace -mcpu with -mdejagnu-cpu

	* gcc.target/powerpc/pr93122.c: Replace -mcpu with -mdejagnu-cpu.
	* gcc.target/powerpc/vsx_mask-count-runnable.c: Likewise.
	* gcc.target/powerpc/vsx_mask-expand-runnable.c: Likewise.
	* gcc.target/powerpc/vsx_mask-extract-runnable.c: Likewise.
	* gcc.target/powerpc/vsx_mask-move-runnable.c: Likewise.
---

diff --git a/gcc/testsuite/gcc.target/powerpc/pr93122.c b/gcc/testsuite/gcc.target/powerpc/pr93122.c
index 8ea4eb6a48bb..97bcb0cea5ff 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr93122.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr93122.c
@@ -1,7 +1,7 @@
 /* PR target/93122 */
 /* { dg-require-effective-target power10_ok } */
 /* { dg-do compile { target lp64 } } */
-/* { dg-options "-fstack-clash-protection -mprefixed -mcpu=power10" } */
+/* { dg-options "-fstack-clash-protection -mprefixed -mdejagnu-cpu=power10" } */
 
 void bar (char *);
 
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c b/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c
index 6ac4ed2173f4..6aa165c675cd 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c
@@ -1,6 +1,6 @@
 /* { dg-do run { target { power10_hw } } } */
 /* { dg-do link { target { ! power10_hw } } } */
-/* { dg-options "-mcpu=power10 -O2" } */
+/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
 /* { dg-require-effective-target { int128 && power10_ok } } */
 
 /* Check that the expected 128-bit instructions are generated if the processor
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx_mask-expand-runnable.c b/gcc/testsuite/gcc.target/powerpc/vsx_mask-expand-runnable.c
index 05fedf77eb90..9fdfa4a8b822 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx_mask-expand-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx_mask-expand-runnable.c
@@ -1,6 +1,6 @@
 /* { dg-do run { target { power10_hw } } } */
 /* { dg-do link { target { ! power10_hw } } } */
-/* { dg-options "-mcpu=power10 -O2" } */
+/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
 /* { dg-require-effective-target { int128 && power10_ok } } */
 
 /* Check that the expected 128-bit instructions are generated if the processor
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx_mask-extract-runnable.c b/gcc/testsuite/gcc.target/powerpc/vsx_mask-extract-runnable.c
index 6e952695905d..a038e56c9cdd 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx_mask-extract-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx_mask-extract-runnable.c
@@ -1,6 +1,6 @@
 /* { dg-do run { target { power10_hw } } } */
 /* { dg-do link { target { ! power10_hw } } } */
-/* { dg-options "-mcpu=power10 -O2" } */
+/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
 /* { dg-require-effective-target { int128 && power10_ok } } */
 
 /* Check that the expected 128-bit instructions are generated if the processor
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx_mask-move-runnable.c b/gcc/testsuite/gcc.target/powerpc/vsx_mask-move-runnable.c
index c2eb53d3bb23..6f87e60ea417 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx_mask-move-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx_mask-move-runnable.c
@@ -1,6 +1,6 @@
 /* { dg-do run { target { power10_hw } } } */
 /* { dg-do link { target { ! power10_hw } } } */
-/* { dg-options "-mcpu=power10 -O2" } */
+/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
 /* { dg-require-effective-target { int128 && power10_ok } } */
 
 /* Check that the expected 128-bit instructions are generated if the processor