From: Peter Maydell <peter.maydell@linaro.org>
Date: Thu, 16 May 2019 12:15:08 +0000 (+0100)
Subject: Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190510' into staging
X-Git-Tag: v4.1.0-rc0~110
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=d8276573da58e8ce78dab8c46dd660efd664bcb7;p=thirdparty%2Fqemu.git

Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190510' into staging

Add CPUClass::tlb_fill.
Improve tlb_vaddr_to_host for use by ARM SVE no-fault loads.

# gpg: Signature made Fri 10 May 2019 19:48:37 BST
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* remotes/rth/tags/pull-tcg-20190510: (27 commits)
  tcg: Use tlb_fill probe from tlb_vaddr_to_host
  tcg: Remove CPUClass::handle_mmu_fault
  tcg: Use CPUClass::tlb_fill in cputlb.c
  target/xtensa: Convert to CPUClass::tlb_fill
  target/unicore32: Convert to CPUClass::tlb_fill
  target/tricore: Convert to CPUClass::tlb_fill
  target/tilegx: Convert to CPUClass::tlb_fill
  target/sparc: Convert to CPUClass::tlb_fill
  target/sh4: Convert to CPUClass::tlb_fill
  target/s390x: Convert to CPUClass::tlb_fill
  target/riscv: Convert to CPUClass::tlb_fill
  target/ppc: Convert to CPUClass::tlb_fill
  target/openrisc: Convert to CPUClass::tlb_fill
  target/nios2: Convert to CPUClass::tlb_fill
  target/moxie: Convert to CPUClass::tlb_fill
  target/mips: Convert to CPUClass::tlb_fill
  target/mips: Tidy control flow in mips_cpu_handle_mmu_fault
  target/mips: Pass a valid error to raise_mmu_exception for user-only
  target/microblaze: Convert to CPUClass::tlb_fill
  target/m68k: Convert to CPUClass::tlb_fill
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---

d8276573da58e8ce78dab8c46dd660efd664bcb7
diff --cc accel/tcg/cputlb.c
index a0833247684,685e0f2ee4e..cdcc3771020
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@@ -855,9 -855,29 +855,28 @@@ static inline ram_addr_t qemu_ram_addr_
      return ram_addr;
  }
  
+ /*
+  * Note: tlb_fill() can trigger a resize of the TLB. This means that all of the
+  * caller's prior references to the TLB table (e.g. CPUTLBEntry pointers) must
+  * be discarded and looked up again (e.g. via tlb_entry()).
+  */
+ static void tlb_fill(CPUState *cpu, target_ulong addr, int size,
+                      MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
+ {
+     CPUClass *cc = CPU_GET_CLASS(cpu);
+     bool ok;
+ 
+     /*
+      * This is not a probe, so only valid return is success; failure
+      * should result in exception + longjmp to the cpu loop.
+      */
+     ok = cc->tlb_fill(cpu, addr, size, access_type, mmu_idx, false, retaddr);
+     assert(ok);
+ }
+ 
  static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
 -                         int mmu_idx,
 -                         target_ulong addr, uintptr_t retaddr,
 -                         bool recheck, MMUAccessType access_type, int size)
 +                         int mmu_idx, target_ulong addr, uintptr_t retaddr,
 +                         MMUAccessType access_type, int size)
  {
      CPUState *cpu = ENV_GET_CPU(env);
      hwaddr mr_offset;