From: Kyrylo Tkachov Date: Thu, 4 May 2023 08:41:46 +0000 (+0100) Subject: aarch64: PR target/99195 annotate more simple binary ops for vec-concat with zero X-Git-Tag: basepoints/gcc-15~9667 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=d840bc5cab39aa3dd8222d72b2cd40942bf91c93;p=thirdparty%2Fgcc.git aarch64: PR target/99195 annotate more simple binary ops for vec-concat with zero More pattern annotations and tests to eliminate redundant vec-concat with zero instructions. These are for the abd family of instructions and the pairwise floating-point max/min and fadd operations too. Bootstrapped and tested on aarch64-none-linux-gnu. gcc/ChangeLog: PR target/99195 * config/aarch64/aarch64-simd.md (aarch64_abd): Rename to... (aarch64_abd): ... This. (fabd3): Rename to... (fabd3): ... This. (aarch64_p): Rename to... (aarch64_p): ... This. (aarch64_faddp): Rename to... (aarch64_faddp): ... This. gcc/testsuite/ChangeLog: PR target/99195 * gcc.target/aarch64/simd/pr99195_1.c: Add testing for more binary ops. * gcc.target/aarch64/simd/pr99195_2.c: Add testing for more binary ops. --- diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index b9473e00093c..511d1e78809d 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -915,7 +915,7 @@ ;; So (ABS:QI (minus:QI 64 -128)) == (ABS:QI (192 or -64 signed)) == 64. ;; Whereas SABD would return 192 (-64 signed) on the above example. ;; Use MINUS ([us]max (op1, op2), [us]min (op1, op2)) instead. -(define_insn "aarch64_abd" +(define_insn "aarch64_abd" [(set (match_operand:VDQ_BHSI 0 "register_operand" "=w") (minus:VDQ_BHSI (USMAX:VDQ_BHSI @@ -1112,7 +1112,7 @@ [(set_attr "type" "neon_arith_acc")] ) -(define_insn "fabd3" +(define_insn "fabd3" [(set (match_operand:VHSDF_HSDF 0 "register_operand" "=w") (abs:VHSDF_HSDF (minus:VHSDF_HSDF @@ -1714,7 +1714,7 @@ }) ;; Pairwise Integer Max/Min operations. -(define_insn "aarch64_p" +(define_insn "aarch64_p" [(set (match_operand:VDQ_BHSI 0 "register_operand" "=w") (unspec:VDQ_BHSI [(match_operand:VDQ_BHSI 1 "register_operand" "w") (match_operand:VDQ_BHSI 2 "register_operand" "w")] @@ -1725,7 +1725,7 @@ ) ;; Pairwise FP Max/Min operations. -(define_insn "aarch64_p" +(define_insn "aarch64_p" [(set (match_operand:VHSDF 0 "register_operand" "=w") (unspec:VHSDF [(match_operand:VHSDF 1 "register_operand" "w") (match_operand:VHSDF 2 "register_operand" "w")] @@ -3595,7 +3595,7 @@ ;; 'across lanes' add. -(define_insn "aarch64_faddp" +(define_insn "aarch64_faddp" [(set (match_operand:VHSDF 0 "register_operand" "=w") (unspec:VHSDF [(match_operand:VHSDF 1 "register_operand" "w") (match_operand:VHSDF 2 "register_operand" "w")] diff --git a/gcc/testsuite/gcc.target/aarch64/simd/pr99195_1.c b/gcc/testsuite/gcc.target/aarch64/simd/pr99195_1.c index 7354a0be4b2f..5801598d4293 100644 --- a/gcc/testsuite/gcc.target/aarch64/simd/pr99195_1.c +++ b/gcc/testsuite/gcc.target/aarch64/simd/pr99195_1.c @@ -57,15 +57,19 @@ OPSIX (T, IS, OS, S, OP6, OP7, OP8, OP9, OP10, OP11) OPSEVEN (T, IS, OS, S, OP1, OP2, OP3, OP4, OP5, OP6, OP7) \ OPSEVEN (T, IS, OS, S, OP8, OP9, OP10, OP11, OP12, OP13, OP14) -OPFOURTEEN (int8, 8, 16, s8, padd, add, sub, mul, and, orr, eor, orn, bic, max, min, hadd, rhadd, hsub) -OPFOURTEEN (int16, 4, 8, s16, padd, add, sub, mul, and, orr, eor, orn, bic, max, min, hadd, rhadd, hsub) -OPFOURTEEN (int32, 2, 4, s32, padd, add, sub, mul, and, orr, eor, orn, bic, max, min, hadd, rhadd, hsub) +#define OPSEVENTEEN(T,IS,OS,S,OP1,OP2,OP3,OP4,OP5,OP6,OP7,OP8,OP9,OP10,OP11,OP12,OP13,OP14,OP15,OP16,OP17) \ +OPSEVEN (T, IS, OS, S, OP1, OP2, OP3, OP4, OP5, OP6, OP7) \ +OPTEN (T, IS, OS, S, OP8, OP9, OP10, OP11, OP12, OP13, OP14, OP15, OP16, OP17) + +OPSEVENTEEN (int8, 8, 16, s8, padd, add, sub, mul, and, orr, eor, orn, bic, max, min, hadd, rhadd, hsub, abd, pmax, pmin) +OPSEVENTEEN (int16, 4, 8, s16, padd, add, sub, mul, and, orr, eor, orn, bic, max, min, hadd, rhadd, hsub, abd, pmax, pmin) +OPSEVENTEEN (int32, 2, 4, s32, padd, add, sub, mul, and, orr, eor, orn, bic, max, min, hadd, rhadd, hsub, abd, pmax, pmin) -OPFOURTEEN (uint8, 8, 16, u8, padd, add, sub, mul, and, orr, eor, orn, bic, max, min, hadd, rhadd, hsub) -OPFOURTEEN (uint16, 4, 8, u16, padd, add, sub, mul, and, orr, eor, orn, bic, max, min, hadd, rhadd, hsub) -OPFOURTEEN (uint32, 2, 4, u32, padd, add, sub, mul, and, orr, eor, orn, bic, max, min, hadd, rhadd, hsub) +OPSEVENTEEN (uint8, 8, 16, u8, padd, add, sub, mul, and, orr, eor, orn, bic, max, min, hadd, rhadd, hsub, abd, pmax, pmin) +OPSEVENTEEN (uint16, 4, 8, u16, padd, add, sub, mul, and, orr, eor, orn, bic, max, min, hadd, rhadd, hsub, abd, pmax, pmin) +OPSEVENTEEN (uint32, 2, 4, u32, padd, add, sub, mul, and, orr, eor, orn, bic, max, min, hadd, rhadd, hsub, abd, pmax, pmin) -OPEIGHT (float32, 2, 4, f32, add, sub, mul, div, max, maxnm, min, minnm) +OPFOURTEEN (float32, 2, 4, f32, add, padd, sub, mul, div, max, maxnm, min, minnm, abd, pmax, pmin, pmaxnm, pminnm) #define UNARY(OT,IT,OP,S) \ OT \ diff --git a/gcc/testsuite/gcc.target/aarch64/simd/pr99195_2.c b/gcc/testsuite/gcc.target/aarch64/simd/pr99195_2.c index 603c5ab1439f..f11f49e00871 100644 --- a/gcc/testsuite/gcc.target/aarch64/simd/pr99195_2.c +++ b/gcc/testsuite/gcc.target/aarch64/simd/pr99195_2.c @@ -53,7 +53,11 @@ OPFIVE (T, IS, OS, S, OP6, OP7, OP8, OP9, OP10) OPFIVE (T, IS, OS, S, OP1, OP2, OP3, OP4, OP5) \ OPSIX (T, IS, OS, S, OP6, OP7, OP8, OP9, OP10, OP11) -OPEIGHT (float16, 4, 8, f16, add, sub, mul, div, max, maxnm, min, minnm) +#define OPTHIRTEEN(T,IS,OS,S,OP1,OP2,OP3,OP4,OP5,OP6,OP7,OP8,OP9,OP10,OP11,OP12,OP13) \ +OPSIX (T, IS, OS, S, OP1, OP2, OP3, OP4, OP5, OP6) \ +OPSEVEN (T, IS, OS, S, OP7, OP8, OP9, OP10, OP11, OP12, OP13) + +OPTHIRTEEN (float16, 4, 8, f16, add, sub, mul, div, max, maxnm, min, minnm, abd, pmax, pmin, pmaxnm, pminnm) #define UNARY(OT,IT,OP,S) \ OT \