From: Pan Li <pan2.li@intel.com>
Date: Wed, 4 Feb 2026 06:00:12 +0000 (+0800)
Subject: RISC-V: Adjust testcase asm check for vx-[56]-i[16|8].c
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=d931a18247130376de4ecd7543934b5a2d9ae287;p=thirdparty%2Fgcc.git

RISC-V: Adjust testcase asm check for vx-[56]-i[16|8].c

Due to middle-end and new param change, adjust the test cases asm check
as it cannot be vectorized.

	PR/target 123916

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c: Adjust the
	asm check to not.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c: Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>
---

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c
index 2209d565d41..a1de51ba172 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c
@@ -34,8 +34,8 @@ DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BOD
 /* { dg-final { scan-assembler {vrem.vx} } } */
 /* { dg-final { scan-assembler {vmax.vx} } } */
 /* { dg-final { scan-assembler {vmin.vx} } } */
-/* { dg-final { scan-assembler {vsadd.vx} } } */
-/* { dg-final { scan-assembler {vssub.vx} } } */
+/* { dg-final { scan-assembler-not {vsadd.vx} } } */
+/* { dg-final { scan-assembler-not {vssub.vx} } } */
 /* { dg-final { scan-assembler {vaadd.vx} { target { any-opts {
      "-mrvv-vector-bits=zvl -mrvv-max-lmul=m1"
      "-mrvv-vector-bits=zvl -mrvv-max-lmul=m2"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c
index 26610a6f839..86f9a29b5f9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c
@@ -34,8 +34,8 @@ DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BOD
 /* { dg-final { scan-assembler {vrem.vx} } } */
 /* { dg-final { scan-assembler {vmax.vx} } } */
 /* { dg-final { scan-assembler {vmin.vx} } } */
-/* { dg-final { scan-assembler {vsadd.vx} } } */
-/* { dg-final { scan-assembler {vssub.vx} } } */
+/* { dg-final { scan-assembler-not {vsadd.vx} } } */
+/* { dg-final { scan-assembler-not {vssub.vx} } } */
 /* { dg-final { scan-assembler {vaadd.vx} { target { no-opts {
      "-mrvv-vector-bits=zvl -mrvv-max-lmul=m1"
      "-mrvv-vector-bits=zvl -mrvv-max-lmul=m2"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
index 326971b4bd0..58730d0a0d4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
@@ -34,8 +34,8 @@ DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BOD
 /* { dg-final { scan-assembler {vrem.vx} } } */
 /* { dg-final { scan-assembler {vmax.vx} } } */
 /* { dg-final { scan-assembler {vmin.vx} } } */
-/* { dg-final { scan-assembler {vsadd.vx} } } */
-/* { dg-final { scan-assembler {vssub.vx} } } */
+/* { dg-final { scan-assembler-not {vsadd.vx} } } */
+/* { dg-final { scan-assembler-not {vssub.vx} } } */
 /* { dg-final { scan-assembler {vaadd.vx} { target { any-opts {
      "-mrvv-vector-bits=zvl -mrvv-max-lmul=m1"
      "-mrvv-vector-bits=zvl -mrvv-max-lmul=m2"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
index c03f23346c0..f1eece7266f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
@@ -34,8 +34,8 @@ DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BOD
 /* { dg-final { scan-assembler {vrem.vx} } } */
 /* { dg-final { scan-assembler {vmax.vx} } } */
 /* { dg-final { scan-assembler {vmin.vx} } } */
-/* { dg-final { scan-assembler {vsadd.vx} } } */
-/* { dg-final { scan-assembler {vssub.vx} } } */
+/* { dg-final { scan-assembler-not {vsadd.vx} } } */
+/* { dg-final { scan-assembler-not {vssub.vx} } } */
 /* { dg-final { scan-assembler {vaadd.vx} { target { any-opts {
      "-mrvv-vector-bits=zvl -mrvv-max-lmul=m1"
      "-mrvv-vector-bits=zvl -mrvv-max-lmul=m2"