From: Kenneth Kasilag Date: Thu, 2 Jul 2026 11:31:11 +0000 (+0000) Subject: qualcommbe: ipq9574: fix MISC2 mode field and cover USXGMII X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=d9a98ed59de0d2c135a7396081499dcf4797298b;p=thirdparty%2Fopenwrt.git qualcommbe: ipq9574: fix MISC2 mode field and cover USXGMII The MISC2 phy mode field is modelled as two bits at the wrong offset: the hardware field is three bits wide and starts one bit lower. The SGMII and 2500BASE-X values only come out right because the power-on default happens to keep the missed bit set, and USXGMII is not programmed at all, leaving the uniphy in its power-on SGMII personality. Model the field at its documented position, add the USXGMII mode value and write the rate field explicitly instead of relying on its power-on default, matching the values the vendor SSDK programs. Signed-off-by: Kenneth Kasilag Link: https://github.com/openwrt/openwrt/pull/24033 Signed-off-by: Robert Marko --- diff --git a/target/linux/qualcommbe/patches-6.18/0360-net-pcs-qcom-ipq9574-set-MISC2-phy-mode-for-USXGMII.patch b/target/linux/qualcommbe/patches-6.18/0360-net-pcs-qcom-ipq9574-set-MISC2-phy-mode-for-USXGMII.patch new file mode 100644 index 00000000000..a0b79d7f3dc --- /dev/null +++ b/target/linux/qualcommbe/patches-6.18/0360-net-pcs-qcom-ipq9574-set-MISC2-phy-mode-for-USXGMII.patch @@ -0,0 +1,52 @@ +From: Kenneth Kasilag +Date: Thu, 02 Jul 2026 00:00:00 +0000 +Subject: [PATCH] net: pcs: qcom-ipq9574: fix MISC2 phy mode field and cover USXGMII + +The MISC2 phy mode field is modelled as two bits at the wrong offset: +the hardware field is three bits wide and starts one bit lower. The +SGMII and 2500BASE-X values only come out right because the power-on +default happens to keep the missed bit set, and USXGMII is not +programmed at all, leaving the uniphy in its power-on SGMII +personality. + +Model the field at its documented position, add the USXGMII mode +value and write the rate field explicitly instead of relying on its +power-on default, matching the values the vendor SSDK programs. + +Signed-off-by: Kenneth Kasilag +--- + drivers/net/pcs/pcs-qcom-ipq9574.c | 14 +++++++++----- + 1 file changed, 10 insertions(+), 4 deletions(-) + +--- a/drivers/net/pcs/pcs-qcom-ipq9574.c ++++ b/drivers/net/pcs/pcs-qcom-ipq9574.c +@@ -29,9 +29,11 @@ + #define PCS_CLKOUT_50M_DIV2_SEL BIT(5) + + #define PCS_MISC2 0x218 +-#define PCS_MISC2_MODE_MASK GENMASK(6, 5) +-#define PCS_MISC2_MODE_SGMII FIELD_PREP(PCS_MISC2_MODE_MASK, 0x1) +-#define PCS_MISC2_MODE_SGMII_PLUS FIELD_PREP(PCS_MISC2_MODE_MASK, 0x2) ++#define PCS_MISC2_RATE_MASK GENMASK(1, 0) ++#define PCS_MISC2_MODE_MASK GENMASK(6, 4) ++#define PCS_MISC2_MODE_SGMII FIELD_PREP(PCS_MISC2_MODE_MASK, 0x3) ++#define PCS_MISC2_MODE_SGMII_PLUS FIELD_PREP(PCS_MISC2_MODE_MASK, 0x5) ++#define PCS_MISC2_MODE_USXGMII FIELD_PREP(PCS_MISC2_MODE_MASK, 0x7) + + #define PCS_MODE_CTRL 0x46c + #define PCS_MODE_SEL_MASK GENMASK(12, 8) +@@ -356,9 +358,13 @@ static int ipq_pcs_config_mode(struct ip + return ret; + } + ++ if (interface == PHY_INTERFACE_MODE_USXGMII) ++ misc2 = PCS_MISC2_MODE_USXGMII; ++ + if (misc2) { + ret = regmap_update_bits(qpcs->regmap, PCS_MISC2, +- PCS_MISC2_MODE_MASK, misc2); ++ PCS_MISC2_MODE_MASK | ++ PCS_MISC2_RATE_MASK, misc2); + if (ret) + return ret; + }