From: Zbigniew Kempczyński Date: Tue, 25 Nov 2025 15:37:33 +0000 (+0100) Subject: drm/xe: Add caching pagetable flag X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=dacda0cf75d5f4aa8da5404c21dc8ab4b7667799;p=thirdparty%2Flinux.git drm/xe: Add caching pagetable flag Introduce device xe_caching_pt flag to selectively turn it on for supported platforms. It allows to eliminate version check and enable this feature for the future platforms. Signed-off-by: Zbigniew Kempczyński Cc: Matthew Auld Reviewed-by: Matthew Auld Signed-off-by: Matthew Auld Link: https://patch.msgid.link/20251125153732.400766-2-zbigniew.kempczynski@intel.com --- diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c index 465cf9fc7ce95..ea02374f8887a 100644 --- a/drivers/gpu/drm/xe/xe_bo.c +++ b/drivers/gpu/drm/xe/xe_bo.c @@ -515,8 +515,7 @@ static struct ttm_tt *xe_ttm_tt_create(struct ttm_buffer_object *ttm_bo, * non-coherent and require a CPU:WC mapping. */ if ((!bo->cpu_caching && bo->flags & XE_BO_FLAG_SCANOUT) || - (xe->info.graphics_verx100 >= 1270 && - bo->flags & XE_BO_FLAG_PAGETABLE)) + (!xe->info.has_cached_pt && bo->flags & XE_BO_FLAG_PAGETABLE)) caching = ttm_write_combined; } diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h index e8de3f807ad9f..9a9a8eb84a786 100644 --- a/drivers/gpu/drm/xe/xe_device_types.h +++ b/drivers/gpu/drm/xe/xe_device_types.h @@ -285,6 +285,8 @@ struct xe_device { u8 has_asid:1; /** @info.has_atomic_enable_pte_bit: Device has atomic enable PTE bit */ u8 has_atomic_enable_pte_bit:1; + /** @info.has_cached_pt: Supports caching pagetable */ + u8 has_cached_pt:1; /** @info.has_device_atomics_on_smem: Supports device atomics on SMEM */ u8 has_device_atomics_on_smem:1; /** @info.has_fan_control: Device supports fan control */ diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c index 4b4c6aa800eca..94abefa3d9ca4 100644 --- a/drivers/gpu/drm/xe/xe_pci.c +++ b/drivers/gpu/drm/xe/xe_pci.c @@ -168,6 +168,7 @@ static const struct xe_device_desc tgl_desc = { .pre_gmdid_media_ip = &media_ip_xem, PLATFORM(TIGERLAKE), .dma_mask_size = 39, + .has_cached_pt = true, .has_display = true, .has_llc = true, .has_sriov = true, @@ -182,6 +183,7 @@ static const struct xe_device_desc rkl_desc = { .pre_gmdid_media_ip = &media_ip_xem, PLATFORM(ROCKETLAKE), .dma_mask_size = 39, + .has_cached_pt = true, .has_display = true, .has_llc = true, .max_gt_per_tile = 1, @@ -197,6 +199,7 @@ static const struct xe_device_desc adl_s_desc = { .pre_gmdid_media_ip = &media_ip_xem, PLATFORM(ALDERLAKE_S), .dma_mask_size = 39, + .has_cached_pt = true, .has_display = true, .has_llc = true, .has_sriov = true, @@ -217,6 +220,7 @@ static const struct xe_device_desc adl_p_desc = { .pre_gmdid_media_ip = &media_ip_xem, PLATFORM(ALDERLAKE_P), .dma_mask_size = 39, + .has_cached_pt = true, .has_display = true, .has_llc = true, .has_sriov = true, @@ -235,6 +239,7 @@ static const struct xe_device_desc adl_n_desc = { .pre_gmdid_media_ip = &media_ip_xem, PLATFORM(ALDERLAKE_N), .dma_mask_size = 39, + .has_cached_pt = true, .has_display = true, .has_llc = true, .has_sriov = true, @@ -663,6 +668,7 @@ static int xe_info_init_early(struct xe_device *xe, xe->info.vram_flags = desc->vram_flags; xe->info.is_dgfx = desc->is_dgfx; + xe->info.has_cached_pt = desc->has_cached_pt; xe->info.has_fan_control = desc->has_fan_control; /* runtime fusing may force flat_ccs to disabled later */ xe->info.has_flat_ccs = desc->has_flat_ccs; diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h index d89ee5d824399..f19f35359696e 100644 --- a/drivers/gpu/drm/xe/xe_pci_types.h +++ b/drivers/gpu/drm/xe/xe_pci_types.h @@ -37,6 +37,7 @@ struct xe_device_desc { u8 require_force_probe:1; u8 is_dgfx:1; + u8 has_cached_pt:1; u8 has_display:1; u8 has_fan_control:1; u8 has_flat_ccs:1;