From: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date: Fri, 20 Apr 2018 16:31:19 +0000 (+0000)
Subject: PR testsuite/85483: Move aarch64/sve/vcond_1.c test to g++.dg/other/
X-Git-Tag: basepoints/gcc-9~51
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=db994ead877220f9f71932b1e16b4945b06aafbd;p=thirdparty%2Fgcc.git

PR testsuite/85483: Move aarch64/sve/vcond_1.c test to g++.dg/other/

I totally botched up this sve test file in 259437.
It needs C++, so move it to g++.dg/other and make it a .C file.
Also adds the target guards to prevent it from running on non-aarch64 targets.

Tested that it passes on aarch64-none-elf and doesn't get run on arm-none-eabi.

Committing to trunk as obvious.

	PR testsuite/85483
	* gcc.target/aarch64/sve/vcond_1.c: Move to...
	* g++.dg/other/sve_vcond_1.C: ... Here.  Add target directives.
	* gcc.target/aarch64/sve/vcond_1_run.c: Move to...
	* g++.dg/other/sve_vcond_1_run.C: ... Here.  Change include file name.

From-SVN: r259526
---

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 8e9787647133..4bc930152b82 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2018-04-20  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR testsuite/85483
+	* gcc.target/aarch64/sve/vcond_1.c: Move to...
+	* g++.dg/other/sve_vcond_1.C: ... Here.  Add target directives.
+	* gcc.target/aarch64/sve/vcond_1_run.c: Move to...
+	* g++.dg/other/sve_vcond_1_run.C: ... Here.  Change include file name.
+
 2018-04-20  H.J. Lu  <hongjiu.lu@intel.com>
 
 	PR target/85469
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/vcond_1.c b/gcc/testsuite/g++.dg/other/sve_vcond_1.C
similarity index 98%
rename from gcc/testsuite/gcc.target/aarch64/sve/vcond_1.c
rename to gcc/testsuite/g++.dg/other/sve_vcond_1.C
index 66208425e2ee..c1ad0b91b0cb 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/vcond_1.c
+++ b/gcc/testsuite/g++.dg/other/sve_vcond_1.C
@@ -1,5 +1,5 @@
-/* { dg-do assemble { target aarch64_asm_sve_ok } } */
-/* { dg-options "-O -msve-vector-bits=256 --save-temps" } */
+/* { dg-do assemble { target { aarch64_asm_sve_ok && { ! ilp32 } } } } */
+/* { dg-options "-march=armv8.2-a+sve -O -msve-vector-bits=256 --save-temps" } */
 
 typedef __INT8_TYPE__ vnx16qi __attribute__((vector_size(32)));
 typedef __INT16_TYPE__ vnx8hi __attribute__((vector_size(32)));
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/vcond_1_run.c b/gcc/testsuite/g++.dg/other/sve_vcond_1_run.C
similarity index 97%
rename from gcc/testsuite/gcc.target/aarch64/sve/vcond_1_run.c
rename to gcc/testsuite/g++.dg/other/sve_vcond_1_run.C
index 72dab3942a96..d01745e68647 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/vcond_1_run.c
+++ b/gcc/testsuite/g++.dg/other/sve_vcond_1_run.C
@@ -2,7 +2,7 @@
 /* { dg-options "-O" } */
 /* { dg-options "-O -msve-vector-bits=256" { target aarch64_sve256_hw } } */
 
-#include "vcond_1.c"
+#include "sve_vcond_1.c"
 
 #define NUM_ELEMS(X) (sizeof (X) / sizeof (X[0]))