From: Marek Vasut Date: Sat, 4 Apr 2026 18:35:01 +0000 (+0200) Subject: ASoC: fsl_sai: Add RX/TX BCLK swap support X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=dc06cf4268a4ad4192fb688ae81c8638df6c8810;p=thirdparty%2Flinux.git ASoC: fsl_sai: Add RX/TX BCLK swap support Add support for setting the Bit Clock Swap bit in CR2 register via new "fsl,sai-bit-clock-swap" DT property. This bit swaps the bit clock used by the transmitter or receiver in asynchronous mode, i.e. makes transmitter use RX_BCLK and TX_SYNC, and vice versa, makes receiver use TX_BCLK and RX_SYNC. Signed-off-by: Marek Vasut Link: https://patch.msgid.link/20260404183547.46509-2-marex@nabladev.com Signed-off-by: Mark Brown --- diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c index bd336d2e4cb38..87a40e2b9fdf7 100644 --- a/sound/soc/fsl/fsl_sai.c +++ b/sound/soc/fsl/fsl_sai.c @@ -355,6 +355,9 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai, unsigned int ofs = sai->soc_data->reg_offset; u32 val_cr2 = 0, val_cr4 = 0; + if (sai->is_bit_clock_swap) + val_cr2 |= FSL_SAI_CR2_BCS; + if (!sai->is_lsb_first) val_cr4 |= FSL_SAI_CR4_MF; @@ -453,7 +456,8 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai, } regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), - FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2); + FSL_SAI_CR2_BCS | FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, + val_cr2); regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4); @@ -1507,6 +1511,7 @@ static int fsl_sai_probe(struct platform_device *pdev) sai->soc_data = of_device_get_match_data(dev); sai->is_lsb_first = of_property_read_bool(np, "lsb-first"); + sai->is_bit_clock_swap = of_property_read_bool(np, "fsl,sai-bit-clock-swap"); base = devm_platform_get_and_ioremap_resource(pdev, 0, &sai->res); if (IS_ERR(base)) diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h index af967833b6eda..6d84e5ff2258e 100644 --- a/sound/soc/fsl/fsl_sai.h +++ b/sound/soc/fsl/fsl_sai.h @@ -118,6 +118,7 @@ /* SAI Transmit and Receive Configuration 2 Register */ #define FSL_SAI_CR2_SYNC BIT(30) +#define FSL_SAI_CR2_BCS BIT(29) #define FSL_SAI_CR2_BCI BIT(28) #define FSL_SAI_CR2_MSEL_MASK (0x3 << 26) #define FSL_SAI_CR2_MSEL_BUS 0 @@ -301,6 +302,7 @@ struct fsl_sai { struct fsl_sai_dl_cfg *dl_cfg; unsigned int dl_cfg_cnt; bool mclk_direction_output; + bool is_bit_clock_swap; unsigned int mclk_id[2]; unsigned int mclk_streams;