From: Uros Bizjak Date: Sun, 25 Aug 2019 19:51:45 +0000 (+0200) Subject: re PR target/91533 (abs pattern generates MMX instructions but fails to call EMMS) X-Git-Tag: releases/gcc-7.5.0~301 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=dcccb54b9134f2fdc69bd0a4abf98d9ef3138140;p=thirdparty%2Fgcc.git re PR target/91533 (abs pattern generates MMX instructions but fails to call EMMS) PR target/91533 Backport from mainline 2019-06-30 Uroš Bizjak * config/i386/sse.md (ssse3_abs2): Rename from abs2. * config/i386/i386-builtin.def (__builtin_ia32_pabsb): Use CODE_FOR_ssse3_absv8qi2. (__builtin_ia32_pabsw): Use CODE_FOR_ssse3_absv4hi2. (__builtin_ia32_pabsd): Use CODE_FOR_ssse3_absv2si2. From-SVN: r274914 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a16f442b3b03..b6b707117928 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,15 @@ +2019-08-25 UroÅ¡ Bizjak + + PR target/91533 + Backport from mainline + 2019-06-30 UroÅ¡ Bizjak + + * config/i386/sse.md (ssse3_abs2): Rename from abs2. + * config/i386/i386-builtin.def (__builtin_ia32_pabsb): + Use CODE_FOR_ssse3_absv8qi2. + (__builtin_ia32_pabsw): Use CODE_FOR_ssse3_absv4hi2. + (__builtin_ia32_pabsd): Use CODE_FOR_ssse3_absv2si2. + 2019-08-21 Richard Biener PR tree-optimization/91510 diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def index eec6a27242ef..35ab29204db9 100644 --- a/gcc/config/i386/i386-builtin.def +++ b/gcc/config/i386/i386-builtin.def @@ -766,11 +766,11 @@ BDESC (OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", I /* SSSE3 */ BDESC (OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI) -BDESC (OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI) +BDESC (OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI) BDESC (OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI) -BDESC (OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI) +BDESC (OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI) BDESC (OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI) -BDESC (OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI) +BDESC (OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI) BDESC (OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI) BDESC (OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 87ae894b235a..9024536b8b1f 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -14930,7 +14930,7 @@ } }) -(define_insn "abs2" +(define_insn "ssse3_abs2" [(set (match_operand:MMXMODEI 0 "register_operand" "=y") (abs:MMXMODEI (match_operand:MMXMODEI 1 "nonimmediate_operand" "ym")))]