From: Christoph Müllner <christoph.muellner@vrull.eu>
Date: Tue, 7 May 2024 20:59:44 +0000 (+0200)
Subject: RISC-V: Add test for sraiw-31 special case
X-Git-Tag: basepoints/gcc-16~9230
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=dd388198b8be52ab378c935fc517a269e0ba741c;p=thirdparty%2Fgcc.git

RISC-V: Add test for sraiw-31 special case

We already optimize a sign-extension of a right-shift by 31 in
<optab>si3_extend.  Let's add a test for that (similar to
zero-extend-1.c).

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/sign-extend-1.c: New test.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---

diff --git a/gcc/testsuite/gcc.target/riscv/sign-extend-1.c b/gcc/testsuite/gcc.target/riscv/sign-extend-1.c
new file mode 100644
index 00000000000..e9056ec0d42
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sign-extend-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target { riscv64*-*-* } } } */
+/* { dg-options "-march=rv64gc -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } {"-O0" "-Os" "-Og" "-Oz" "-flto" } } */
+
+signed long
+foo1 (int i)
+{
+  return i >> 31;
+}
+/* { dg-final { scan-assembler "sraiw\ta\[0-9\],a\[0-9\],31" } } */
+
+/* { dg-final { scan-assembler-not "srai\t" } } */
+/* { dg-final { scan-assembler-not "srli\t" } } */
+/* { dg-final { scan-assembler-not "srliw\t" } } */