From: Palmer Dabbelt <palmer@rivosinc.com>
Date: Thu, 5 Sep 2024 03:34:31 +0000 (-0600)
Subject: [PATCH] RISC-V: Make the setCC/REE tests robust to instruction selection
X-Git-Tag: basepoints/gcc-16~6088
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=de3ca363811a3974e4398ecdb1db2274efd61a1c;p=thirdparty%2Fgcc.git

[PATCH] RISC-V: Make the setCC/REE tests robust to instruction selection

These tests were checking that the output of the setCC instruction was bit
flipped, but it looks like they're really designed to test that
redundant sign extension elimination fires on conditionals from function
inputs.  Jeff just posed a patch to clean this code up with trips up on
the arbitrary xori/snez instruction selection decision changing, so
let's just robustify the tests.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/sge.c: Adjust regex to match the input.
	* gcc.target/riscv/sgeu.c: Likewise.
	* gcc.target/riscv/sle.c: Likewise.
	* gcc.target/riscv/sleu.c: Likewise.
---

diff --git a/gcc/testsuite/gcc.target/riscv/sge.c b/gcc/testsuite/gcc.target/riscv/sge.c
index 5f7e7ae82db..70f934c4d0f 100644
--- a/gcc/testsuite/gcc.target/riscv/sge.c
+++ b/gcc/testsuite/gcc.target/riscv/sge.c
@@ -8,5 +8,5 @@ sge (int x, int y)
   return x >= y;
 }
 
-/* { dg-final { scan-assembler "\\sxori\\sa0,a0,1\n\\sret\n" } } */
+/* { dg-final { scan-assembler "slt\\sa0,a0,a1" } } */
 /* { dg-final { scan-assembler-not "andi|sext\\.w" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sgeu.c b/gcc/testsuite/gcc.target/riscv/sgeu.c
index 234b9aa52bd..0ff21cfe5e0 100644
--- a/gcc/testsuite/gcc.target/riscv/sgeu.c
+++ b/gcc/testsuite/gcc.target/riscv/sgeu.c
@@ -8,5 +8,5 @@ sgeu (unsigned int x, unsigned int y)
   return x >= y;
 }
 
-/* { dg-final { scan-assembler "\\sxori\\sa0,a0,1\n\\sret\n" } } */
+/* { dg-final { scan-assembler "sltu\\sa0,a0,a1" } } */
 /* { dg-final { scan-assembler-not "andi|sext\\.w" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sle.c b/gcc/testsuite/gcc.target/riscv/sle.c
index 3259c191598..770840d0564 100644
--- a/gcc/testsuite/gcc.target/riscv/sle.c
+++ b/gcc/testsuite/gcc.target/riscv/sle.c
@@ -8,5 +8,5 @@ sle (int x, int y)
   return x <= y;
 }
 
-/* { dg-final { scan-assembler "\\sxori\\sa0,a0,1\n\\sret\n" } } */
+/* { dg-final { scan-assembler "sgt\\sa0,a0,a1" } } */
 /* { dg-final { scan-assembler-not "andi|sext\\.w" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sleu.c b/gcc/testsuite/gcc.target/riscv/sleu.c
index 301b8c32eb7..ae00ccc2067 100644
--- a/gcc/testsuite/gcc.target/riscv/sleu.c
+++ b/gcc/testsuite/gcc.target/riscv/sleu.c
@@ -8,5 +8,5 @@ sleu (unsigned int x, unsigned int y)
   return x <= y;
 }
 
-/* { dg-final { scan-assembler "\\sxori\\sa0,a0,1\n\\sret\n" } } */
+/* { dg-final { scan-assembler "sgtu\\sa0,a0,a1"} } */
 /* { dg-final { scan-assembler-not "andi|sext\\.w" } } */