From: Uros Bizjak Date: Fri, 13 Nov 2009 19:51:52 +0000 (+0100) Subject: re PR target/41900 (call *%esp shouldn't be generated because of CPU errata) X-Git-Tag: releases/gcc-4.3.5~297 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=de5f895ff34981e72cd1b8da28d4b851c8469620;p=thirdparty%2Fgcc.git re PR target/41900 (call *%esp shouldn't be generated because of CPU errata) 2009-11-13 Uros Bizjak PR target/41900 (*call_pop_1, *call_1, *call_value_pop_1, *call_value_1): Use "lsm" as operand 1 constraint. * config/i386/predicates.md (call_insn_operand): Depend on index_register_operand to avoid %esp register. 2009-11-13 Uros Bizjak Revert: 2009-11-05 Uros Bizjak PR target/41900 * config/i386/i386.h (ix86_arch_indices) : New. (TARGET_CALL_ESP): New define. * config/i386/i386.c (initial_ix86_tune_features): Initialize X86_ARCH_CALL_ESP. * config/i386/i386.md (*call_pop_1_esp, *call_1_esp, *call_value_pop_1_esp, *call_value_1_esp): Rename from *call_pop_1, *call_1, *call_value_pop_1 and *call_value_1. Depend on TARGET_CALL_ESP. (*call_pop_1, *call_1, *call_value_pop_1, *call_value_1): New patterns, use "lsm" as operand 1 constraint. * config/i386/predicates.md (call_insn_operand): Depend on index_register_operand for !TARGET_CALL_ESP to avoid %esp register. From-SVN: r154171 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index bcaa6cf82bf3..50045a5bc252 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,30 @@ +2009-11-13 Uros Bizjak + + PR target/41900 + (*call_pop_1, *call_1, *call_value_pop_1, *call_value_1): Use "lsm" + as operand 1 constraint. + * config/i386/predicates.md (call_insn_operand): Depend on + index_register_operand to avoid %esp register. + +2009-11-13 Uros Bizjak + + Revert: + 2009-11-05 Uros Bizjak + + PR target/41900 + * config/i386/i386.h (ix86_arch_indices) : New. + (TARGET_CALL_ESP): New define. + * config/i386/i386.c (initial_ix86_tune_features): Initialize + X86_ARCH_CALL_ESP. + * config/i386/i386.md (*call_pop_1_esp, *call_1_esp, + *call_value_pop_1_esp, *call_value_1_esp): Rename from *call_pop_1, + *call_1, *call_value_pop_1 and *call_value_1. Depend on + TARGET_CALL_ESP. + (*call_pop_1, *call_1, *call_value_pop_1, *call_value_1): + New patterns, use "lsm" as operand 1 constraint. + * config/i386/predicates.md (call_insn_operand): Depend on + index_register_operand for !TARGET_CALL_ESP to avoid %esp register. + 2009-11-04 Jason Merrill PR c++/36912 diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 97d77d396eeb..d9f9b8cd3e44 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -1451,11 +1451,6 @@ unsigned int ix86_arch_features[X86_ARCH_LAST] = { /* X86_ARCH_BSWAP: Byteswap was added for 80486. */ ~m_386, - - /* X86_ARCH_CALL_ESP: P6 processors will jump to the address after - the decrement (so they will execute return address as code). See - Pentium Pro errata 70, Pentium 2 errata A33, Pentium 3 errata E17. */ - ~(m_386 | m_486 | m_PENT | m_PPRO), }; static const unsigned int x86_accumulate_outgoing_args diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 849226d7b511..1d76c467b95d 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -372,7 +372,6 @@ enum ix86_arch_indices { X86_ARCH_CMPXCHG8B, X86_ARCH_XADD, X86_ARCH_BSWAP, - X86_ARCH_CALL_ESP, X86_ARCH_LAST }; @@ -384,7 +383,6 @@ extern unsigned int ix86_arch_features[X86_ARCH_LAST]; #define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B] #define TARGET_XADD ix86_arch_features[X86_ARCH_XADD] #define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP] -#define TARGET_CALL_ESP ix86_arch_features[X86_ARCH_CALL_ESP] #define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387) diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 59ba88528aea..6d571726aac3 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -14654,6 +14654,10 @@ ;; checked for calls. This is a bug in the generic code, but it isn't that ;; easy to fix. Ignore it for now and be prepared to fix things up. +;; P6 processors will jump to the address after the decrement when %esp +;; is used as a call operand, so they will execute return address as a code. +;; See Pentium Pro errata 70, Pentium 2 errata A33 and Pentium 3 errata E17. + ;; Call subroutine returning no value. (define_expand "call_pop" @@ -14682,25 +14686,12 @@ } [(set_attr "type" "call")]) -(define_insn "*call_pop_1_esp" - [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm")) - (match_operand:SI 1 "" "")) - (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) - (match_operand:SI 2 "immediate_operand" "i")))] - "!TARGET_64BIT && TARGET_CALL_ESP && !SIBLING_CALL_P (insn)" -{ - if (constant_call_address_operand (operands[0], Pmode)) - return "call\t%P0"; - return "call\t%A0"; -} - [(set_attr "type" "call")]) - (define_insn "*call_pop_1" [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "lsm")) (match_operand:SI 1 "" "")) (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_operand:SI 2 "immediate_operand" "i")))] - "!TARGET_64BIT && !TARGET_CALL_ESP && !SIBLING_CALL_P (insn)" + "!TARGET_64BIT && !SIBLING_CALL_P (insn)" { if (constant_call_address_operand (operands[0], Pmode)) return "call\t%P0"; @@ -14753,21 +14744,10 @@ } [(set_attr "type" "call")]) -(define_insn "*call_1_esp" - [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm")) - (match_operand 1 "" ""))] - "!TARGET_64BIT && TARGET_CALL_ESP && !SIBLING_CALL_P (insn)" -{ - if (constant_call_address_operand (operands[0], Pmode)) - return "call\t%P0"; - return "call\t%A0"; -} - [(set_attr "type" "call")]) - (define_insn "*call_1" [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "lsm")) (match_operand 1 "" ""))] - "!TARGET_64BIT && !TARGET_CALL_ESP && !SIBLING_CALL_P (insn)" + "!TARGET_64BIT && !SIBLING_CALL_P (insn)" { if (constant_call_address_operand (operands[0], Pmode)) return "call\t%P0"; @@ -21087,27 +21067,13 @@ } [(set_attr "type" "callv")]) -(define_insn "*call_value_pop_1_esp" - [(set (match_operand 0 "" "") - (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm")) - (match_operand:SI 2 "" ""))) - (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) - (match_operand:SI 3 "immediate_operand" "i")))] - "!TARGET_64BIT && TARGET_CALL_ESP && !SIBLING_CALL_P (insn)" -{ - if (constant_call_address_operand (operands[1], Pmode)) - return "call\t%P1"; - return "call\t%A1"; -} - [(set_attr "type" "callv")]) - (define_insn "*call_value_pop_1" [(set (match_operand 0 "" "") (call (mem:QI (match_operand:SI 1 "call_insn_operand" "lsm")) (match_operand:SI 2 "" ""))) (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_operand:SI 3 "immediate_operand" "i")))] - "!TARGET_64BIT && !TARGET_CALL_ESP && !SIBLING_CALL_P (insn)" + "!TARGET_64BIT && !SIBLING_CALL_P (insn)" { if (constant_call_address_operand (operands[1], Pmode)) return "call\t%P1"; @@ -21155,23 +21121,11 @@ } [(set_attr "type" "callv")]) -(define_insn "*call_value_1_esp" - [(set (match_operand 0 "" "") - (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm")) - (match_operand:SI 2 "" "")))] - "!TARGET_64BIT && TARGET_CALL_ESP && !SIBLING_CALL_P (insn)" -{ - if (constant_call_address_operand (operands[1], Pmode)) - return "call\t%P1"; - return "call\t%A1"; -} - [(set_attr "type" "callv")]) - (define_insn "*call_value_1" [(set (match_operand 0 "" "") (call (mem:QI (match_operand:SI 1 "call_insn_operand" "lsm")) (match_operand:SI 2 "" "")))] - "!TARGET_64BIT && !TARGET_CALL_ESP && !SIBLING_CALL_P (insn)" + "!TARGET_64BIT && !SIBLING_CALL_P (insn)" { if (constant_call_address_operand (operands[1], Pmode)) return "call\t%P1"; diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md index aac032d2c198..5a81557c6392 100644 --- a/gcc/config/i386/predicates.md +++ b/gcc/config/i386/predicates.md @@ -545,9 +545,7 @@ ;; Test for a valid operand for a call instruction. (define_predicate "call_insn_operand" (ior (match_operand 0 "constant_call_address_operand") - (ior (and (match_operand 0 "register_no_elim_operand") - (ior (match_test "TARGET_CALL_ESP") - (match_operand 0 "index_register_operand"))) + (ior (match_operand 0 "index_register_operand") (match_operand 0 "memory_operand")))) ;; Similarly, but for tail calls, in which we cannot allow memory references.