From: Jeff Law <jlaw@ventanamicro.com>
Date: Fri, 27 Jun 2025 13:00:15 +0000 (-0600)
Subject: [RISC-V][PR target/119971] Avoid losing shift count masking
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=de6124c9e5ed472f567b51fa76f18335cdddbbaf;p=thirdparty%2Fgcc.git

[RISC-V][PR target/119971] Avoid losing shift count masking

Fix typo spotted by Bernhard Reutner-Fischer.

	PR target/119971

gcc/testsuite/
	* gcc.target/riscv/pr119971.c: Fix typo.
---

diff --git a/gcc/testsuite/gcc.target/riscv/pr119971.c b/gcc/testsuite/gcc.target/riscv/pr119971.c
index c3f23b05ec3..0d73d4ca3f1 100644
--- a/gcc/testsuite/gcc.target/riscv/pr119971.c
+++ b/gcc/testsuite/gcc.target/riscv/pr119971.c
@@ -1,6 +1,6 @@
 /* { dg-do compile { target rv64 } } */
 /* { dg-options "-march=rv64gcb -mabi=lp64" } */
-/* { dg-skip-if "" { *-*-* } { "-O0" "-g" "-Oz" "-Os" } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Oz" "-Os" } } */
 
 __attribute__ ((noipa)) unsigned
 foo (unsigned b, unsigned e, unsigned i)