From: Yang Wang <kevinyang.wang@amd.com>
Date: Wed, 10 Dec 2025 12:27:42 +0000 (+0800)
Subject: drm/amd/pm: add smu pcie dpm cap & width convert helper
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=deacae541a7210c675f1013ed5a276886b2f48d6;p=thirdparty%2Fkernel%2Flinux.git

drm/amd/pm: add smu pcie dpm cap & width convert helper

define following heler to convert pmfw pcie dpm index to smu index.
- SMU_DPM_PCIE_GEN_IDX(gen)
- SMU_DPM_PCIE_WIDTH_IDX(width)

Signed-off-by: Yang Wang <kevinyang.wang@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index 88e9699d9cc1..ef5aa4e42a17 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -1317,3 +1317,53 @@ int smu_cmn_print_pcie_levels(struct smu_context *smu,
 
 	return 0;
 }
+
+int smu_cmn_dpm_pcie_gen_idx(int gen)
+{
+	int ret;
+
+	switch (gen) {
+	case 1 ... 5:
+		ret = gen - 1;
+		break;
+	default:
+		ret = -1;
+		break;
+	}
+
+	return ret;
+}
+
+int smu_cmn_dpm_pcie_width_idx(int width)
+{
+	int ret;
+
+	switch (width) {
+	case 1:
+		ret = 1;
+		break;
+	case 2:
+		ret = 2;
+		break;
+	case 4:
+		ret = 3;
+		break;
+	case 8:
+		ret = 4;
+		break;
+	case 12:
+		ret = 5;
+		break;
+	case 16:
+		ret = 6;
+		break;
+	case 32:
+		ret = 7;
+		break;
+	default:
+		ret = -1;
+		break;
+	}
+
+	return ret;
+}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
index f458125e8d4e..3a8d05afa654 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
@@ -93,6 +93,9 @@
 		header->structure_size = sizeof(*tmp);                          \
 	} while (0)
 
+#define SMU_DPM_PCIE_GEN_IDX(gen)	smu_cmn_dpm_pcie_gen_idx((gen))
+#define SMU_DPM_PCIE_WIDTH_IDX(width)	smu_cmn_dpm_pcie_width_idx((width))
+
 extern const int link_speed[];
 
 /* Helper to Convert from PCIE Gen 1/2/3/4/5/6 to 0.1 GT/s speed units */
@@ -212,6 +215,9 @@ int smu_cmn_print_pcie_levels(struct smu_context *smu,
 			       uint32_t cur_gen, uint32_t cur_lane,
 			       char *buf, int *offset);
 
+int smu_cmn_dpm_pcie_gen_idx(int gen);
+int smu_cmn_dpm_pcie_width_idx(int width);
+
 /*SMU gpu metrics */
 
 /* Attribute ID mapping */