From: Richard Sandiford <richard.sandiford@arm.com>
Date: Tue, 4 Mar 2025 17:49:31 +0000 (+0000)
Subject: aarch64: Add missing simd requirements for INS [PR118531]
X-Git-Tag: releases/gcc-14.3.0~418
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=df9c10d18b5b1323efb5f7823c31a259859d87a4;p=thirdparty%2Fgcc.git

aarch64: Add missing simd requirements for INS [PR118531]

In g:b096a6ebe9d9f9fed4c105f6555f724eb32af95c I'd forgotten
to gate some uses of INS on TARGET_SIMD.

gcc/
	PR target/118531
	* config/aarch64/aarch64.md (*insv_reg<mode>_<SUBDI_BITS>)
	(*aarch64_bfi<GPI:mode><ALLX:mode>_<SUBDI_BITS>)
	(*aarch64_bfidi<ALLX:mode>_subreg_<SUBDI_BITS>): Add missing
	simd requirements.

gcc/testsuite/
	* gcc.target/aarch64/ins_bitfield_1a.c: New test.
	* gcc.target/aarch64/ins_bitfield_3a.c: Likewise.
	* gcc.target/aarch64/ins_bitfield_5a.c: Likewise.

(cherry picked from commit 1b8820421488d220a95f651b51175d618063c48c)
---

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index dbde066f747..a08523a2b07 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -6130,7 +6130,8 @@
       return "ins\t%0.<bits_etype>[%1], %2.<bits_etype>[0]";
     return "ins\t%0.<bits_etype>[%1], %w2";
   }
-  [(set_attr "type" "bfm,neon_ins_q,neon_ins_q")]
+  [(set_attr "type" "bfm,neon_ins_q,neon_ins_q")
+   (set_attr "arch" "*,simd,simd")]
 )
 
 (define_insn "*insv_reg<mode>"
@@ -6163,7 +6164,8 @@
     operands[2] = lowpart_subreg (<GPI:MODE>mode, operands[2],
 				  <ALLX:MODE>mode);
   }
-  [(set_attr "type" "bfm,neon_ins_q,neon_ins_q")]
+  [(set_attr "type" "bfm,neon_ins_q,neon_ins_q")
+   (set_attr "arch" "*,simd,simd")]
 )
 
 (define_insn "*aarch64_bfi<GPI:mode><ALLX:mode>4"
@@ -6195,7 +6197,8 @@
   {
     operands[2] = lowpart_subreg (DImode, operands[3], <ALLX:MODE>mode);
   }
-  [(set_attr "type" "bfm,neon_ins_q,neon_ins_q")]
+  [(set_attr "type" "bfm,neon_ins_q,neon_ins_q")
+   (set_attr "arch" "*,simd,simd")]
 )
 
 ;;  Match a bfi instruction where the shift of OP3 means that we are
diff --git a/gcc/testsuite/gcc.target/aarch64/ins_bitfield_1a.c b/gcc/testsuite/gcc.target/aarch64/ins_bitfield_1a.c
new file mode 100644
index 00000000000..028d4aa1e89
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/ins_bitfield_1a.c
@@ -0,0 +1,8 @@
+/* { dg-do assemble } */
+/* { dg-options "-O2 --save-temps" } */
+
+#pragma GCC target "+nosimd"
+
+#include "ins_bitfield_1.c"
+
+/* { dg-final { scan-assembler-not {\tins\t} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/ins_bitfield_3a.c b/gcc/testsuite/gcc.target/aarch64/ins_bitfield_3a.c
new file mode 100644
index 00000000000..1c153667a8d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/ins_bitfield_3a.c
@@ -0,0 +1,8 @@
+/* { dg-do assemble } */
+/* { dg-options "-O2 --save-temps" } */
+
+#pragma GCC target "+nosimd"
+
+#include "ins_bitfield_3.c"
+
+/* { dg-final { scan-assembler-not {\tins\t} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/ins_bitfield_5a.c b/gcc/testsuite/gcc.target/aarch64/ins_bitfield_5a.c
new file mode 100644
index 00000000000..f6bdde97f98
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/ins_bitfield_5a.c
@@ -0,0 +1,8 @@
+/* { dg-do assemble } */
+/* { dg-options "-O2 --save-temps" } */
+
+#pragma GCC target "+nosimd"
+
+#include "ins_bitfield_5.c"
+
+/* { dg-final { scan-assembler-not {\tins\t} } } */