From: Ulrich Weigand <uweigand@de.ibm.com>
Date: Tue, 15 Oct 2002 18:34:36 +0000 (+0000)
Subject: re PR target/7370 (ICE in fixup_var_refs_1 on s390x)
X-Git-Tag: releases/gcc-3.2.1~155
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=dfa7dd0f02f62089695101fda363dd92b8bd6903;p=thirdparty%2Fgcc.git

re PR target/7370 (ICE in fixup_var_refs_1 on s390x)

	PR target/7370
	* config/s390/s390.md ("*addsi3_inv"): New pattern.

	PR target/8232
	* config/s390/s390.md ("cmpstrsi"): Convert length operand
	from SImode to Pmode.

From-SVN: r58171
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 375c055f0a3b..9873a34c6a5b 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2002-10-15  Ulrich Weigand  <uweigand@de.ibm.com>
+
+	PR target/7370
+	* config/s390/s390.md ("*addsi3_inv"): New pattern.
+
+	PR target/8232
+	* config/s390/s390.md ("cmpstrsi"): Convert length operand
+	from SImode to Pmode.
+
 2002-10-15  Janis Johnson  <janis187@us.ibm.com>
 
 	* doc/install.texi: Formatting changes for conformance to HTML 4.01.
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 366a5b30c773..fce55208df4c 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -2111,15 +2111,12 @@
 	  reg1 = gen_reg_rtx (DImode);
         }  
 
-      if (! CONSTANT_P (len))
-          len = force_reg (Pmode, len);
-
       /* Load up the address+length pairs.  */
       emit_move_insn (gen_highpart (Pmode, reg0), addr0); 
-      emit_move_insn (gen_lowpart (Pmode, reg0), len);
+      convert_move (gen_lowpart (Pmode, reg0), len, 1);
 
       emit_move_insn (gen_highpart (Pmode, reg1), addr1);
-      emit_move_insn (gen_lowpart (Pmode, reg1), len);
+      convert_move (gen_lowpart (Pmode, reg1), len, 1);
 
       /* Compare! */
       if (TARGET_64BIT) 
@@ -3226,6 +3223,19 @@
   [(set_attr "op_type"  "RR,RI,RX")
    (set_attr "atype"    "reg,reg,mem")])
 
+(define_insn "*addsi3_inv"
+  [(set (match_operand:SI 0 "register_operand" "=d,d,d")
+        (plus:SI (match_operand:SI 1 "general_operand" "%d,K,m")
+                 (match_operand:SI 2 "register_operand" "0,0,0")))
+   (clobber (reg:CC 33))]
+  ""
+  "@
+   ar\\t%0,%1
+   ahi\\t%0,%h1
+   a\\t%0,%1"
+  [(set_attr "op_type"  "RR,RI,RX")
+   (set_attr "atype"    "reg,reg,mem")])
+
 (define_insn "*la_31"
   [(set (match_operand:SI 0 "register_operand" "=d")
         (match_operand:QI 1 "address_operand" "p"))]