From: Alice Carlotti Date: Wed, 29 Apr 2026 16:00:28 +0000 (+0100) Subject: aarch64: Remove unused operand ADDR_SIMM9_2 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=dfaa6336059d14499aefbd433de5b2b473ad33e9;p=thirdparty%2Fbinutils-gdb.git aarch64: Remove unused operand ADDR_SIMM9_2 This has been unused since the original handling for load/store register (unscaled) instructions was removed in c8f89a3423101b25. --- diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 618fdb9da44..0b72fc1a54f 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -7782,14 +7782,11 @@ parse_operands (char *str, const aarch64_opcode *opcode) break; case AARCH64_OPND_ADDR_SIMM9: - case AARCH64_OPND_ADDR_SIMM9_2: case AARCH64_OPND_ADDR_SIMM11: case AARCH64_OPND_ADDR_SIMM13: po_misc_or_fail (parse_address (&str, info)); if (info->addr.pcrel || info->addr.offset.is_reg - || (!info->addr.preind && !info->addr.postind) - || (operands[i] == AARCH64_OPND_ADDR_SIMM9_2 - && info->addr.writeback)) + || (!info->addr.preind && !info->addr.postind)) { set_syntax_error (_("invalid addressing mode")); goto failure; @@ -9749,7 +9746,6 @@ fix_insn (fixS *fixP, uint32_t flags, offsetT value) case AARCH64_OPND_ADDR_SIMM7: case AARCH64_OPND_ADDR_SIMM9: - case AARCH64_OPND_ADDR_SIMM9_2: case AARCH64_OPND_ADDR_SIMM10: case AARCH64_OPND_ADDR_UIMM12: case AARCH64_OPND_ADDR_SIMM11: diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 2fdd3da49ce..222de5f49ab 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -738,13 +738,6 @@ enum aarch64_opnd AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */ AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */ AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */ - AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is - negative or unaligned and there is - no writeback allowed. This operand code - is only used to support the programmer- - friendly feature of using LDR/STR as the - the mnemonic name for LDUR/STUR instructions - wherever there is no ambiguity. */ AARCH64_OPND_ADDR_SIMM10, /* Address of signed 10-bit immediate. */ AARCH64_OPND_ADDR_SIMM11, /* Address with a signed 11-bit (multiple of 16) immediate. */ diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c index 4dff5ea4993..a5533c43421 100644 --- a/opcodes/aarch64-asm-2.c +++ b/opcodes/aarch64-asm-2.c @@ -1001,7 +1001,6 @@ aarch64_insert_operand (const aarch64_operand *self, return aarch64_ins_addr_regoff (self, info, code, inst, errors); case AARCH64_OPND_ADDR_SIMM7: case AARCH64_OPND_ADDR_SIMM9: - case AARCH64_OPND_ADDR_SIMM9_2: case AARCH64_OPND_ADDR_SIMM11: case AARCH64_OPND_ADDR_SIMM13: return aarch64_ins_addr_simm (self, info, code, inst, errors); diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c index 0938f4a846a..69bf6f90564 100644 --- a/opcodes/aarch64-dis-2.c +++ b/opcodes/aarch64-dis-2.c @@ -37989,7 +37989,6 @@ aarch64_extract_operand (const aarch64_operand *self, return aarch64_ext_addr_regoff (self, info, code, inst, errors); case AARCH64_OPND_ADDR_SIMM7: case AARCH64_OPND_ADDR_SIMM9: - case AARCH64_OPND_ADDR_SIMM9_2: case AARCH64_OPND_ADDR_SIMM11: case AARCH64_OPND_ADDR_SIMM13: return aarch64_ext_addr_simm (self, info, code, inst, errors); diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c index 85b763f9766..fb8f664d195 100644 --- a/opcodes/aarch64-opc-2.c +++ b/opcodes/aarch64-opc-2.c @@ -127,7 +127,6 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_ADDRESS, "ADDR_REGOFF", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an address with register offset"}, {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm7,FLD_index2}, "an address with 7-bit signed immediate offset"}, {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM9", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm9,FLD_index}, "an address with 9-bit signed immediate offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM9_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm9,FLD_index}, "an address with 9-bit negative or unaligned immediate offset"}, {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_S_imm10,FLD_imm9,FLD_index}, "an address with an optional 10-bit scaled, signed immediate offset"}, {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM11", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm7,FLD_index2}, "an address with 11-bit signed immediate (multiple of 16) offset"}, {AARCH64_OPND_CLASS_ADDRESS, "ADDR_UIMM12", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm12}, "an address with scaled, unsigned immediate offset"}, diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 3586a2d9146..3beecc00fe3 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -2347,18 +2347,6 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, } break; - case AARCH64_OPND_ADDR_SIMM9_2: - /* Unscaled signed 9 bits immediate offset, which has to be negative - or unaligned. */ - size = aarch64_get_qualifier_esize (qualifier); - if ((value_in_range_p (opnd->addr.offset.imm, 0, 255) - && !value_aligned_p (opnd->addr.offset.imm, size)) - || value_in_range_p (opnd->addr.offset.imm, -256, -1)) - return true; - set_other_error (mismatch_detail, idx, - _("negative or unaligned offset expected")); - return false; - case AARCH64_OPND_ADDR_SIMM10: /* Scaled signed 10 bits immediate offset. */ if (!value_in_range_p (opnd->addr.offset.imm, -4096, 4088)) @@ -4952,7 +4940,6 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_ADDR_SIMM7: case AARCH64_OPND_ADDR_SIMM9: - case AARCH64_OPND_ADDR_SIMM9_2: case AARCH64_OPND_ADDR_SIMM10: case AARCH64_OPND_ADDR_SIMM11: case AARCH64_OPND_ADDR_SIMM13: diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 08982543e1f..fc57f83b120 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -8122,8 +8122,6 @@ const struct aarch64_opcode aarch64_opcode_table[] = "an address with 7-bit signed immediate offset") \ Y(ADDRESS, addr_simm, "ADDR_SIMM9", 0, F(FLD_imm9,FLD_index), \ "an address with 9-bit signed immediate offset") \ - Y(ADDRESS, addr_simm, "ADDR_SIMM9_2", 0, F(FLD_imm9,FLD_index), \ - "an address with 9-bit negative or unaligned immediate offset") \ Y(ADDRESS, addr_simm10, "ADDR_SIMM10", 0, F(FLD_Rn,FLD_S_imm10,FLD_imm9,FLD_index),\ "an address with an optional 10-bit scaled, signed immediate offset") \ Y(ADDRESS, addr_simm, "ADDR_SIMM11", 0, F(FLD_imm7,FLD_index2),\