From: Kyrylo Tkachov Date: Mon, 24 Apr 2023 08:43:55 +0000 (+0100) Subject: [3/4] aarch64: Convert UABAL and SABAL patterns to standard RTL codes X-Git-Tag: basepoints/gcc-15~9948 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=e0472ed5aeeb908cb34be57a74c520c90bcb79d8;p=thirdparty%2Fgcc.git [3/4] aarch64: Convert UABAL and SABAL patterns to standard RTL codes With the SABDL and UABDL patterns converted, the accumulating forms of them UABAL and SABAL are not much more complicated. There's an accumulator argument that we, err, accumulate into with a PLUS once all the widening is done. Some necessary renaming of patterns relating to the removal of UNSPEC_SABAL and UNSPEC_UABAL is included. Bootstrapped and tested on aarch64-none-linux-gnu. gcc/ChangeLog: * config/aarch64/aarch64-simd.md (aarch64_abal): Rename to... (aarch64_abal): ... This. Use RTL codes instead of unspec. (sadv16qi): Rename to... (sadv16qi): ... This. Adjust for the above. * config/aarch64/aarch64-sve.md (sad): Rename to... (sad): ... This. Adjust for the above. * config/aarch64/aarch64.md (UNSPEC_SABAL, UNSPEC_UABAL): Delete. * config/aarch64/iterators.md (ABAL): Delete. (sur): Remove handling of UNSPEC_SABAL and UNSPEC_UABAL. --- diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 6c628681a6d7..51bb6cf357c4 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -952,14 +952,20 @@ } ) -(define_insn "aarch64_abal" +(define_insn "aarch64_abal" [(set (match_operand: 0 "register_operand" "=w") - (unspec: [(match_operand:VD_BHSI 2 "register_operand" "w") - (match_operand:VD_BHSI 3 "register_operand" "w") - (match_operand: 1 "register_operand" "0")] - ABAL))] + (plus: + (zero_extend: + (minus:VD_BHSI + (USMAX:VD_BHSI + (match_operand:VD_BHSI 2 "register_operand" "w") + (match_operand:VD_BHSI 3 "register_operand" "w")) + (:VD_BHSI + (match_dup 2) + (match_dup 3)))) + (match_operand: 1 "register_operand" "0")))] "TARGET_SIMD" - "abal\t%0., %2., %3." + "abal\t%0., %2., %3." [(set_attr "type" "neon_arith_acc")] ) @@ -1004,10 +1010,10 @@ ;; but for TARGET_DOTPROD still emits a UDOT as the absolute difference is ;; unsigned. -(define_expand "sadv16qi" +(define_expand "sadv16qi" [(use (match_operand:V4SI 0 "register_operand")) - (unspec:V16QI [(use (match_operand:V16QI 1 "register_operand")) - (use (match_operand:V16QI 2 "register_operand"))] ABAL) + (USMAX:V16QI (match_operand:V16QI 1 "register_operand") + (match_operand:V16QI 2 "register_operand")) (use (match_operand:V4SI 3 "register_operand"))] "TARGET_SIMD" { @@ -1015,18 +1021,18 @@ { rtx ones = force_reg (V16QImode, CONST1_RTX (V16QImode)); rtx abd = gen_reg_rtx (V16QImode); - emit_insn (gen_aarch64_abdv16qi (abd, operands[1], operands[2])); + emit_insn (gen_aarch64_abdv16qi (abd, operands[1], operands[2])); emit_insn (gen_udot_prodv16qi (operands[0], abd, ones, operands[3])); DONE; } rtx reduc = gen_reg_rtx (V8HImode); - emit_insn (gen_aarch64_abdl2v16qi (reduc, operands[1], + emit_insn (gen_aarch64_abdl2v16qi (reduc, operands[1], operands[2])); - emit_insn (gen_aarch64_abalv8qi (reduc, reduc, - gen_lowpart (V8QImode, operands[1]), - gen_lowpart (V8QImode, - operands[2]))); - emit_insn (gen_aarch64_adalpv8hi (operands[3], operands[3], reduc)); + emit_insn (gen_aarch64_abalv8qi (reduc, reduc, + gen_lowpart (V8QImode, operands[1]), + gen_lowpart (V8QImode, + operands[2]))); + emit_insn (gen_aarch64_adalpv8hi (operands[3], operands[3], reduc)); emit_move_insn (operands[0], operands[3]); DONE; } diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index 7533b9566861..b11b55f7ac71 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -6955,16 +6955,16 @@ ;; [SU]ABD diff.b, p0/m, op1.b, op2.b ;; MOVPRFX op0, op3 // If necessary ;; UDOT op0.s, diff.b, ones.b -(define_expand "sad" +(define_expand "sad" [(use (match_operand:SVE_FULL_SDI 0 "register_operand")) - (unspec: [(use (match_operand: 1 "register_operand")) - (use (match_operand: 2 "register_operand"))] ABAL) + (USMAX: (match_operand: 1 "register_operand") + (match_operand: 2 "register_operand")) (use (match_operand:SVE_FULL_SDI 3 "register_operand"))] "TARGET_SVE" { rtx ones = force_reg (mode, CONST1_RTX (mode)); rtx diff = gen_reg_rtx (mode); - emit_insn (gen_abd_3 (diff, operands[1], operands[2])); + emit_insn (gen_abd_3 (diff, operands[1], operands[2])); emit_insn (gen_udot_prod (operands[0], diff, ones, operands[3])); DONE; } diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 1b2bdf5c5506..426eb85d2db4 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -204,7 +204,6 @@ UNSPEC_PRLG_STK UNSPEC_REV UNSPEC_RBIT - UNSPEC_SABAL UNSPEC_SABAL2 UNSPEC_SADALP UNSPEC_SCVTF @@ -226,7 +225,6 @@ UNSPEC_TLSLE24 UNSPEC_TLSLE32 UNSPEC_TLSLE48 - UNSPEC_UABAL UNSPEC_UABAL2 UNSPEC_UADALP UNSPEC_UCVTF diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index bd4415d6008d..0195cdc545e1 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -2567,9 +2567,6 @@ ;; Int Iterators. ;; ------------------------------------------------------------------- -;; The unspec codes for the SABAL, UABAL AdvancedSIMD instructions. -(define_int_iterator ABAL [UNSPEC_SABAL UNSPEC_UABAL]) - ;; The unspec codes for the SABAL2, UABAL2 AdvancedSIMD instructions. (define_int_iterator ABAL2 [UNSPEC_SABAL2 UNSPEC_UABAL2]) @@ -3354,7 +3351,6 @@ (UNSPEC_SRHADD "sr") (UNSPEC_URHADD "ur") (UNSPEC_SHSUB "s") (UNSPEC_UHSUB "u") (UNSPEC_ADDHN "") (UNSPEC_RADDHN "r") - (UNSPEC_SABAL "s") (UNSPEC_UABAL "u") (UNSPEC_SABAL2 "s") (UNSPEC_UABAL2 "u") (UNSPEC_SADALP "s") (UNSPEC_UADALP "u") (UNSPEC_SUBHN "") (UNSPEC_RSUBHN "r")