From: Jani Nikula Date: Wed, 8 May 2024 15:47:53 +0000 (+0300) Subject: drm/i915: pass dev_priv explicitly to TRANS_VRR_FLIPLINE X-Git-Tag: v6.11-rc1~141^2~20^2~354 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=e050e2acedcfd82b472cb40e9a2e7b762f7997ed;p=thirdparty%2Flinux.git drm/i915: pass dev_priv explicitly to TRANS_VRR_FLIPLINE Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_VRR_FLIPLINE register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/fd8b6a7c71ba908a55a7b40dc54a1d4cf920056c.1715183162.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 05cbd6e4fc60e..e7709b06b92c4 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -224,7 +224,8 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state) crtc_state->vrr.vmax - 1); intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder), trans_vrr_ctl(crtc_state)); - intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder), crtc_state->vrr.flipline - 1); + intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(dev_priv, cpu_transcoder), + crtc_state->vrr.flipline - 1); } void intel_vrr_send_push(const struct intel_crtc_state *crtc_state) @@ -311,7 +312,8 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, trans_vrr_ctl); if (trans_vrr_ctl & VRR_CTL_FLIP_LINE_EN) { - crtc_state->vrr.flipline = intel_de_read(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder)) + 1; + crtc_state->vrr.flipline = intel_de_read(dev_priv, + TRANS_VRR_FLIPLINE(dev_priv, cpu_transcoder)) + 1; crtc_state->vrr.vmax = intel_de_read(dev_priv, TRANS_VRR_VMAX(dev_priv, cpu_transcoder)) + 1; crtc_state->vrr.vmin = intel_de_read(dev_priv, diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index a4313f3180e06..b581e0920c244 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1302,7 +1302,7 @@ #define _TRANS_VRR_FLIPLINE_B 0x61438 #define _TRANS_VRR_FLIPLINE_C 0x62438 #define _TRANS_VRR_FLIPLINE_D 0x63438 -#define TRANS_VRR_FLIPLINE(trans) _MMIO_TRANS2(dev_priv, trans, \ +#define TRANS_VRR_FLIPLINE(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \ _TRANS_VRR_FLIPLINE_A) #define VRR_FLIPLINE_MASK REG_GENMASK(19, 0)