From: João Marcos Costa Date: Wed, 7 Jan 2026 15:14:35 +0000 (+0100) Subject: u-boot: relocate SRC_URI_RISCV into recipe X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=e07cf74374f0462d2ba2bd78e83a19b6a90f2cc3;p=thirdparty%2Fopenembedded%2Fopenembedded-core.git u-boot: relocate SRC_URI_RISCV into recipe In a custom u-boot recipe that requires u-boot-common.inc, the config fragments end up in SRC_URI. However, the custom recipe's FILESPATH does not contain the path to oe-core's u-boot directory (as expected), which leads to the error below: ERROR: .../build/../meta-custom/recipes-bsp/u-boot/u-boot-custom_2025.10.bb: Unable to get checksum for u-boot-custom SRC_URI entry u-boot-riscv-isa_clear.cfg: file could not be found The following paths were searched: (...) Move SRC_URI_RISCV - along with the appends - out of the common definitions. Signed-off-by: João Marcos Costa Signed-off-by: Antonin Godard Signed-off-by: Richard Purdie --- diff --git a/meta/recipes-bsp/u-boot/u-boot-common.inc b/meta/recipes-bsp/u-boot/u-boot-common.inc index 79ddde3f5c..5e2ec08c30 100644 --- a/meta/recipes-bsp/u-boot/u-boot-common.inc +++ b/meta/recipes-bsp/u-boot/u-boot-common.inc @@ -16,18 +16,6 @@ SRCREV = "127a42c7257a6ffbbd1575ed1cbaa8f5408a44b3" SRC_URI = "git://source.denx.de/u-boot/u-boot.git;protocol=https;branch=master;tag=v${PV}" -SRC_URI_RISCV = "\ - file://u-boot-riscv-isa_clear.cfg \ - ${@bb.utils.contains ("TUNE_FEATURES", "a", "file://u-boot-riscv-isa_a.cfg", "", d)} \ - ${@bb.utils.contains ("TUNE_FEATURES", "f", "file://u-boot-riscv-isa_f.cfg", "", d)} \ - ${@bb.utils.contains ("TUNE_FEATURES", "d", "file://u-boot-riscv-isa_d.cfg", "", d)} \ - ${@bb.utils.contains_any("TUNE_FEATURES", "b zbb", "file://u-boot-riscv-isa_zbb.cfg", "", d)} \ - ${@bb.utils.contains ("TUNE_FEATURES", "zicbom", "file://u-boot-riscv-isa_zicbom.cfg", "", d)} \ - " - -SRC_URI:append:riscv32 = "${SRC_URI_RISCV}" -SRC_URI:append:riscv64 = "${SRC_URI_RISCV}" - B = "${WORKDIR}/build" inherit pkgconfig diff --git a/meta/recipes-bsp/u-boot/u-boot_2026.01.bb b/meta/recipes-bsp/u-boot/u-boot_2026.01.bb index 25f264c961..5259fd5832 100644 --- a/meta/recipes-bsp/u-boot/u-boot_2026.01.bb +++ b/meta/recipes-bsp/u-boot/u-boot_2026.01.bb @@ -6,3 +6,15 @@ DEPENDS += "bc-native dtc-native gnutls-native python3-pyelftools-native" # workarounds for aarch64 kvm qemu boot regressions SRC_URI:append:qemuarm64 = " file://disable-CONFIG_BLOBLIST.cfg" SRC_URI:append:genericarm64 = " file://disable-CONFIG_BLOBLIST.cfg" + +SRC_URI_RISCV = "\ + file://u-boot-riscv-isa_clear.cfg \ + ${@bb.utils.contains ("TUNE_FEATURES", "a", "file://u-boot-riscv-isa_a.cfg", "", d)} \ + ${@bb.utils.contains ("TUNE_FEATURES", "f", "file://u-boot-riscv-isa_f.cfg", "", d)} \ + ${@bb.utils.contains ("TUNE_FEATURES", "d", "file://u-boot-riscv-isa_d.cfg", "", d)} \ + ${@bb.utils.contains_any("TUNE_FEATURES", "b zbb", "file://u-boot-riscv-isa_zbb.cfg", "", d)} \ + ${@bb.utils.contains ("TUNE_FEATURES", "zicbom", "file://u-boot-riscv-isa_zicbom.cfg", "", d)} \ + " + +SRC_URI:append:riscv32 = "${SRC_URI_RISCV}" +SRC_URI:append:riscv64 = "${SRC_URI_RISCV}"