From: Aldy Hernandez <aldyh@redhat.com>
Date: Tue, 11 Sep 2012 12:28:02 +0000 (+0000)
Subject: re PR middle-end/54149 (write introduction incorrect wrt the C11 memory model)
X-Git-Tag: misc/gccgo-go1_1_2~939
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=e0a6637cbdc4fa4a0ce37e2bce10dc7932a1c5e8;p=thirdparty%2Fgcc.git

re PR middle-end/54149 (write introduction incorrect wrt the C11 memory model)

        PR middle-end/54149
        * tree-ssa-loop-im.c (execute_sm_if_changed_flag_set): Only set
        flag for writes.

From-SVN: r191179
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index c4b237c284b1..b1ac091e2bc6 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2012-09-11  Aldy Hernandez  <aldyh@redhat.com>
+
+	PR middle-end/54149
+	* tree-ssa-loop-im.c (execute_sm_if_changed_flag_set): Only set
+	flag for writes.
+
 2012-09-11  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
 
 	PR tree-optimization/55492
diff --git a/gcc/testsuite/gcc.dg/simulate-thread/speculative-store-4.c b/gcc/testsuite/gcc.dg/simulate-thread/speculative-store-4.c
new file mode 100644
index 000000000000..59f81b756be5
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/simulate-thread/speculative-store-4.c
@@ -0,0 +1,54 @@
+/* { dg-do link } */
+/* { dg-options "--param allow-store-data-races=0" } */
+/* { dg-final { simulate-thread } } */
+
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "simulate-thread.h"
+
+/* PR 54139 */
+/* Test that speculative stores do not happen for --param
+   allow-store-data-races=0.  */
+
+int g_13=1, insns=1;
+
+__attribute__((noinline))
+void simulate_thread_main()
+{
+  int l_245;
+
+  /* Since g_13 is unilaterally set positive above, there should be
+     no store to g_13 below.  */
+  for (l_245 = 0; l_245 <= 1; l_245 += 1)
+    for (; g_13 <= 0; g_13 = 1)
+      ;
+}
+
+int main()
+{
+  simulate_thread_main ();
+  simulate_thread_done ();
+  return 0;
+}
+
+void simulate_thread_other_threads ()
+{
+  ++g_13;
+  ++insns;
+}
+
+int simulate_thread_step_verify ()
+{
+  return 0;
+}
+
+int simulate_thread_final_verify ()
+{
+  if (g_13 != insns)
+    {
+      printf("FAIL: g_13 was incorrectly cached\n");
+      return 1;
+    }
+  return 0;
+}
diff --git a/gcc/tree-ssa-loop-im.c b/gcc/tree-ssa-loop-im.c
index 0f61631cc793..67cab3a31ae7 100644
--- a/gcc/tree-ssa-loop-im.c
+++ b/gcc/tree-ssa-loop-im.c
@@ -2113,9 +2113,14 @@ execute_sm_if_changed_flag_set (struct loop *loop, mem_ref_p ref)
       gimple_stmt_iterator gsi;
       gimple stmt;
 
-      gsi = gsi_for_stmt (loc->stmt);
-      stmt = gimple_build_assign (flag, boolean_true_node);
-      gsi_insert_after (&gsi, stmt, GSI_CONTINUE_LINKING);
+      /* Only set the flag for writes.  */
+      if (is_gimple_assign (loc->stmt)
+	  && gimple_assign_lhs_ptr (loc->stmt) == loc->ref)
+	{
+	  gsi = gsi_for_stmt (loc->stmt);
+	  stmt = gimple_build_assign (flag, boolean_true_node);
+	  gsi_insert_after (&gsi, stmt, GSI_CONTINUE_LINKING);
+	}
     }
   VEC_free (mem_ref_loc_p, heap, locs);
   return flag;