From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date: Mon, 13 Nov 2023 11:58:51 +0000 (+0800)
Subject: RISC-V: Adapt VLS init tests
X-Git-Tag: basepoints/gcc-15~4749
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=e0cacaabca30208f4ed05abddf48ff821374a0c6;p=thirdparty%2Fgcc.git

RISC-V: Adapt VLS init tests

Realize that init tests are wrong by my previous mistakes.
Fix them and committed.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vls/def.h: Fix init test.
	* gcc.target/riscv/rvv/autovec/vls/init-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/init-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/init-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/init-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/init-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/init-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/init-7.c: Ditto.
---

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
index 2e91b9a9664a..9cc3656e710e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
@@ -437,7 +437,7 @@ typedef double v512df __attribute__ ((vector_size (4096)));
   void init_##TYPE1##_##TYPE2##_##NUM (VARS##NUM (TYPE2, __VA_ARGS__),         \
 				       TYPE2 *__restrict out)                  \
   {                                                                            \
-    TYPE1 v = {INIT##NUM (__VA_ARGS__)};                                       \
+    TYPE1 v = {__VA_ARGS__};                                                   \
     *(TYPE1 *) out = v;                                                        \
   }
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-1.c
index aec2c6e5e5fb..0f78ae0ebe26 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-1.c
@@ -43,4 +43,4 @@ DEF_INIT (v128uqi, uint8_t, 128, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
 	  113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126,
 	  127)
 
-/* { dg-final { scan-assembler-times {vslide1down\.vx} 494 } } */
+/* { dg-final { scan-assembler-times {vid\.v} 14 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-2.c
index f9c58aef5538..f27c395441b2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-2.c
@@ -45,4 +45,4 @@ DEF_INIT (v128uhi, uint16_t, 128, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
 	  113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126,
 	  127)
 
-/* { dg-final { scan-assembler-times {vslide1down\.vx} 494 } } */
+/* { dg-final { scan-assembler-times {vid\.vx} 494 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-3.c
index eb970c7b042f..df15bd7300f4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-3.c
@@ -24,4 +24,4 @@ DEF_INIT (v128hf, _Float16, 128, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
 	  113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126,
 	  127)
 
-/* { dg-final { scan-assembler-times {vfslide1down\.vf} 247 } } */
+/* { dg-final { scan-assembler-times {vle16\.v} 7 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-4.c
index fedeb445a2be..09bdbd19cc00 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-4.c
@@ -45,4 +45,4 @@ DEF_INIT (v128usi, uint32_t, 128, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
 	  113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126,
 	  127)
 
-/* { dg-final { scan-assembler-times {vslide1down\.vx} 494 } } */
+/* { dg-final { scan-assembler-times {vid\.v} 14 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-5.c
index c93ac524c880..65ca8cb41e36 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-5.c
@@ -23,4 +23,4 @@ DEF_INIT (v128sf, float, 128, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
 	  100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113,
 	  114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127)
 
-/* { dg-final { scan-assembler-times {vfslide1down\.vf} 247 } } */
+/* { dg-final { scan-assembler-times {vle32\.v} 7 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-6.c
index 304539f48686..9cd36ce2ec11 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-6.c
@@ -45,4 +45,4 @@ DEF_INIT (v128udi, uint64_t, 128, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
 	  113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126,
 	  127)
 
-/* { dg-final { scan-assembler-times {vslide1down\.vx} 494 } } */
+/* { dg-final { scan-assembler-times {vid\.v} 14 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-7.c
index 4b966010dca2..ad337054f3ac 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-7.c
@@ -23,4 +23,4 @@ DEF_INIT (v128df, double, 128, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
 	  100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113,
 	  114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127)
 
-/* { dg-final { scan-assembler-times {vfslide1down\.vf} 247 } } */
+/* { dg-final { scan-assembler-times {vle64\.v} 7 } } */