From: Petar Jovanovic Date: Wed, 4 Apr 2018 09:51:05 +0000 (+0200) Subject: mips64: use register numbers instead of aliases for inline assembly X-Git-Tag: VALGRIND_3_14_0~131 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=e14452877f502152b736ba9281658fb35355c842;p=thirdparty%2Fvalgrind.git mips64: use register numbers instead of aliases for inline assembly There is an inconsistency in MIPS tools for N32/N64 related to register aliases. To avoid ambiguity, use register numbers instead of aliases where needed. --- diff --git a/VEX/priv/guest_mips_helpers.c b/VEX/priv/guest_mips_helpers.c index 4f74593789..af047ad9c1 100644 --- a/VEX/priv/guest_mips_helpers.c +++ b/VEX/priv/guest_mips_helpers.c @@ -484,47 +484,47 @@ HWord mips_dirtyhelper_rdhwr ( UInt rd ) #define ASM_VOLATILE_UNARY32(inst) \ __asm__ volatile(".set push" "\n\t" \ ".set hardfloat" "\n\t" \ - "cfc1 $t0, $31" "\n\t" \ + "cfc1 $8, $31" "\n\t" \ "ctc1 %2, $31" "\n\t" \ "mtc1 %1, $f20" "\n\t" \ #inst" $f20, $f20" "\n\t" \ "cfc1 %0, $31" "\n\t" \ - "ctc1 $t0, $31" "\n\t" \ + "ctc1 $8, $31" "\n\t" \ ".set pop" "\n\t" \ : "=r" (ret) \ : "r" (loFsVal), "r" (fcsr) \ - : "t0", "$f20" \ + : "$8", "$f20" \ ); #define ASM_VOLATILE_UNARY32_DOUBLE(inst) \ __asm__ volatile(".set push" "\n\t" \ ".set hardfloat" "\n\t" \ - "cfc1 $t0, $31" "\n\t" \ + "cfc1 $8, $31" "\n\t" \ "ctc1 %2, $31" "\n\t" \ "ldc1 $f20, 0(%1)" "\n\t" \ #inst" $f20, $f20" "\n\t" \ "cfc1 %0, $31" "\n\t" \ - "ctc1 $t0, $31" "\n\t" \ + "ctc1 $8, $31" "\n\t" \ ".set pop" "\n\t" \ : "=r" (ret) \ : "r" (&fsVal), "r" (fcsr) \ - : "t0", "$f20", "$f21" \ + : "$8", "$f20", "$f21" \ ); #define ASM_VOLATILE_UNARY64(inst) \ __asm__ volatile(".set push" "\n\t" \ ".set hardfloat" "\n\t" \ ".set fp=64" "\n\t" \ - "cfc1 $t0, $31" "\n\t" \ + "cfc1 $8, $31" "\n\t" \ "ctc1 %2, $31" "\n\t" \ "ldc1 $f24, 0(%1)" "\n\t" \ #inst" $f24, $f24" "\n\t" \ "cfc1 %0, $31" "\n\t" \ - "ctc1 $t0, $31" "\n\t" \ + "ctc1 $8, $31" "\n\t" \ ".set pop" "\n\t" \ : "=r" (ret) \ : "r" (&(addr[fs])), "r" (fcsr) \ - : "t0", "$f24" \ + : "$8", "$f24" \ ); #define ASM_VOLATILE_MSA_UNARY(inst) \ @@ -549,49 +549,49 @@ HWord mips_dirtyhelper_rdhwr ( UInt rd ) #define ASM_VOLATILE_BINARY32(inst) \ __asm__ volatile(".set push" "\n\t" \ ".set hardfloat" "\n\t" \ - "cfc1 $t0, $31" "\n\t" \ + "cfc1 $8, $31" "\n\t" \ "ctc1 %3, $31" "\n\t" \ "mtc1 %1, $f20" "\n\t" \ "mtc1 %2, $f22" "\n\t" \ #inst" $f20, $f20, $f22" "\n\t" \ "cfc1 %0, $31" "\n\t" \ - "ctc1 $t0, $31" "\n\t" \ + "ctc1 $8, $31" "\n\t" \ ".set pop" "\n\t" \ : "=r" (ret) \ : "r" (loFsVal), "r" (loFtVal), "r" (fcsr) \ - : "t0", "$f20", "$f22" \ + : "$8", "$f20", "$f22" \ ); #define ASM_VOLATILE_BINARY32_DOUBLE(inst) \ __asm__ volatile(".set push" "\n\t" \ ".set hardfloat" "\n\t" \ - "cfc1 $t0, $31" "\n\t" \ + "cfc1 $8, $31" "\n\t" \ "ctc1 %3, $31" "\n\t" \ "ldc1 $f20, 0(%1)" "\n\t" \ "ldc1 $f22, 0(%2)" "\n\t" \ #inst" $f20, $f20, $f22" "\n\t" \ "cfc1 %0, $31" "\n\t" \ - "ctc1 $t0, $31" "\n\t" \ + "ctc1 $8, $31" "\n\t" \ ".set pop" "\n\t" \ : "=r" (ret) \ : "r" (&fsVal), "r" (&ftVal), "r" (fcsr) \ - : "t0", "$f20", "$f21", "$f22", "$f23" \ + : "$8", "$f20", "$f21", "$f22", "$f23" \ ); #define ASM_VOLATILE_BINARY64(inst) \ __asm__ volatile(".set push" "\n\t" \ ".set hardfloat" "\n\t" \ - "cfc1 $t0, $31" "\n\t" \ + "cfc1 $8, $31" "\n\t" \ "ctc1 %3, $31" "\n\t" \ "ldc1 $f24, 0(%1)" "\n\t" \ "ldc1 $f26, 0(%2)" "\n\t" \ #inst" $f24, $f24, $f26" "\n\t" \ "cfc1 %0, $31" "\n\t" \ - "ctc1 $t0, $31" "\n\t" \ + "ctc1 $8, $31" "\n\t" \ ".set pop" "\n\t" \ : "=r" (ret) \ : "r" (&(addr[fs])), "r" (&(addr[ft])), "r" (fcsr) \ - : "t0", "$f24", "$f26" \ + : "$8", "$f24", "$f26" \ ); #define ASM_VOLATILE_MSA_BINARY(inst) \