From: David Lechner Date: Thu, 11 Dec 2025 22:32:10 +0000 (-0600) Subject: clk: mediatek: remove CLOCK_PARENT_* aliases X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=e21edf2620749f1390c9ac3ebe329a6fd261c65a;p=thirdparty%2Fu-boot.git clk: mediatek: remove CLOCK_PARENT_* aliases Remove the CLOCK_* aliases of the CLOCK_PARENT_* macros. One name for each flag is sufficient. Signed-off-by: David Lechner --- diff --git a/drivers/clk/mediatek/clk-mt7981.c b/drivers/clk/mediatek/clk-mt7981.c index 6130c93d5e6..2fdb1845e9f 100644 --- a/drivers/clk/mediatek/clk-mt7981.c +++ b/drivers/clk/mediatek/clk-mt7981.c @@ -521,7 +521,7 @@ static const struct mtk_clk_tree mt7981_topckgen_clk_tree = { .fclks = top_fixed_clks, .fdivs = top_fixed_divs, .muxes = top_muxes, - .flags = CLK_BYPASS_XTAL | CLK_TOPCKGEN, + .flags = CLK_BYPASS_XTAL | CLK_PARENT_TOPCKGEN, }; static const struct mtk_clk_tree mt7981_infracfg_clk_tree = { @@ -531,7 +531,7 @@ static const struct mtk_clk_tree mt7981_infracfg_clk_tree = { .fdivs = infra_fixed_divs, .muxes = infra_muxes, .gates = infracfg_gates, - .flags = CLK_INFRASYS, + .flags = CLK_PARENT_INFRASYS, }; static const struct udevice_id mt7981_fixed_pll_compat[] = { diff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c index cf298af644c..16db5877056 100644 --- a/drivers/clk/mediatek/clk-mt7986.c +++ b/drivers/clk/mediatek/clk-mt7986.c @@ -519,7 +519,7 @@ static const struct mtk_clk_tree mt7986_fixed_pll_clk_tree = { .fdivs_offs = CLK_APMIXED_NR_CLK, .xtal_rate = 40 * MHZ, .fclks = fixed_pll_clks, - .flags = CLK_APMIXED, + .flags = CLK_PARENT_APMIXED, }; static const struct mtk_clk_tree mt7986_topckgen_clk_tree = { @@ -528,7 +528,7 @@ static const struct mtk_clk_tree mt7986_topckgen_clk_tree = { .fclks = top_fixed_clks, .fdivs = top_fixed_divs, .muxes = top_muxes, - .flags = CLK_BYPASS_XTAL | CLK_TOPCKGEN, + .flags = CLK_BYPASS_XTAL | CLK_PARENT_TOPCKGEN, }; static const struct mtk_clk_tree mt7986_infracfg_clk_tree = { @@ -538,7 +538,7 @@ static const struct mtk_clk_tree mt7986_infracfg_clk_tree = { .fdivs = infra_fixed_divs, .muxes = infra_muxes, .gates = infracfg_gates, - .flags = CLK_INFRASYS, + .flags = CLK_PARENT_INFRASYS, }; static const struct udevice_id mt7986_fixed_pll_compat[] = { diff --git a/drivers/clk/mediatek/clk-mt7987.c b/drivers/clk/mediatek/clk-mt7987.c index b662d680b15..caee8bf43e4 100644 --- a/drivers/clk/mediatek/clk-mt7987.c +++ b/drivers/clk/mediatek/clk-mt7987.c @@ -46,7 +46,7 @@ static const struct mtk_fixed_clk apmixedsys_mtk_plls[] = { static const struct mtk_clk_tree mt7987_fixed_pll_clk_tree = { .fdivs_offs = ARRAY_SIZE(apmixedsys_mtk_plls), .fclks = apmixedsys_mtk_plls, - .flags = CLK_APMIXED, + .flags = CLK_PARENT_APMIXED, .xtal_rate = 40 * MHZ, }; @@ -442,7 +442,7 @@ static const struct mtk_clk_tree mt7987_topckgen_clk_tree = { .muxes_offs = CLK_TOP_NETSYS_SEL, .fdivs = topckgen_mtk_fixed_factors, .muxes = topckgen_mtk_muxes, - .flags = CLK_BYPASS_XTAL | CLK_TOPCKGEN, + .flags = CLK_BYPASS_XTAL | CLK_PARENT_TOPCKGEN, .xtal_rate = MT7987_XTAL_RATE, }; diff --git a/drivers/clk/mediatek/clk-mt7988.c b/drivers/clk/mediatek/clk-mt7988.c index c6da42f970b..bfbf401eb12 100644 --- a/drivers/clk/mediatek/clk-mt7988.c +++ b/drivers/clk/mediatek/clk-mt7988.c @@ -773,7 +773,7 @@ static const struct mtk_gate infracfg_mtk_gates[] = { static const struct mtk_clk_tree mt7988_fixed_pll_clk_tree = { .fdivs_offs = ARRAY_SIZE(apmixedsys_mtk_plls), .fclks = apmixedsys_mtk_plls, - .flags = CLK_APMIXED, + .flags = CLK_PARENT_APMIXED, .xtal_rate = 40 * MHZ, }; @@ -783,7 +783,7 @@ static const struct mtk_clk_tree mt7988_topckgen_clk_tree = { .fclks = topckgen_mtk_fixed_clks, .fdivs = topckgen_mtk_fixed_factors, .muxes = topckgen_mtk_muxes, - .flags = CLK_BYPASS_XTAL | CLK_TOPCKGEN, + .flags = CLK_BYPASS_XTAL | CLK_PARENT_TOPCKGEN, .xtal_rate = 40 * MHZ, }; diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index 89479001ba8..8ce7e52fd60 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -41,11 +41,6 @@ #define CLK_PARENT_MIXED BIT(8) #define CLK_PARENT_MASK GENMASK(8, 4) -/* alias to reference clk type */ -#define CLK_APMIXED CLK_PARENT_APMIXED -#define CLK_TOPCKGEN CLK_PARENT_TOPCKGEN -#define CLK_INFRASYS CLK_PARENT_INFRASYS - #define ETHSYS_HIFSYS_RST_CTRL_OFS 0x34 /* struct mtk_pll_data - hardware-specific PLLs data */