From: Juzhe-Zhong Date: Wed, 31 May 2023 10:47:03 +0000 (+0800) Subject: RISC-V: Remove FRM for vfncvt.rod instruction X-Git-Tag: basepoints/gcc-15~8701 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=e2a326227977dd361bb3b52b8409ebc57240a2a7;p=thirdparty%2Fgcc.git RISC-V: Remove FRM for vfncvt.rod instruction Apparently, vfncvt.rod rounding mode is encoded, so we don't need FRM. gcc/ChangeLog: * config/riscv/vector.md: Remove FRM. Signed-off-by: Pan Li --- diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index cd696da5d898..60f052bcec92 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -7290,10 +7290,8 @@ (match_operand 5 "const_int_operand" " i, i, i, i, i, i") (match_operand 6 "const_int_operand" " i, i, i, i, i, i") (match_operand 7 "const_int_operand" " i, i, i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i, i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM) - (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (unspec: [(float_truncate: (match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))] UNSPEC_ROD)