From: Richard Henderson Date: Fri, 26 Sep 2025 00:11:26 +0000 (-0700) Subject: target/arm: Add GPCCR fields from ARM revision L.b X-Git-Tag: v10.2.0-rc1~74^2~8 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=e2c25b123d48a9bb2d723f19a595914690e348b0;p=thirdparty%2Fqemu.git target/arm: Add GPCCR fields from ARM revision L.b Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier Message-id: 20250926001134.295547-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 2b9585dc80..41414ac22b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1995,13 +1995,19 @@ FIELD(V7M_VPR, MASK01, 16, 4) FIELD(V7M_VPR, MASK23, 20, 4) FIELD(GPCCR, PPS, 0, 3) +FIELD(GPCCR, RLPAD, 5, 1) +FIELD(GPCCR, NSPAD, 6, 1) +FIELD(GPCCR, SPAD, 7, 1) FIELD(GPCCR, IRGN, 8, 2) FIELD(GPCCR, ORGN, 10, 2) FIELD(GPCCR, SH, 12, 2) FIELD(GPCCR, PGS, 14, 2) FIELD(GPCCR, GPC, 16, 1) FIELD(GPCCR, GPCP, 17, 1) +FIELD(GPCCR, TBGPCD, 18, 1) +FIELD(GPCCR, NSO, 19, 1) FIELD(GPCCR, L0GPTSZ, 20, 4) +FIELD(GPCCR, APPSAA, 24, 1) FIELD(MFAR, FPA, 12, 40) FIELD(MFAR, NSE, 62, 1)