From: Alexander Stein Date: Fri, 13 Mar 2026 07:07:31 +0000 (+0100) Subject: clk: imx: fracn-gppll: Add 333.333333 MHz support X-Git-Tag: v7.1-rc1~59^2~1^4^2~9 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=e2f8311a6aa5f809bb62de61888292e58087fd21;p=thirdparty%2Fkernel%2Fstable.git clk: imx: fracn-gppll: Add 333.333333 MHz support Some parallel panels have a pixelclk of 33.30 MHz. Add support for 333.333333 MHz so a by 10 divider can be used to derive the exact pixelclk. Signed-off-by: Alexander Stein Reviewed-by: Abel Vesa Reviewed-by: Peng Fan Link: https://patch.msgid.link/20260313070740.585043-2-alexander.stein@ew.tq-group.com Signed-off-by: Abel Vesa --- diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c index 89ed7749bf47e..fe6ee77ba1485 100644 --- a/drivers/clk/imx/clk-fracn-gppll.c +++ b/drivers/clk/imx/clk-fracn-gppll.c @@ -88,6 +88,7 @@ static const struct imx_fracn_gppll_rate_table fracn_tbl[] = { PLL_FRACN_GP(445333333U, 167, 0, 1, 0, 9), PLL_FRACN_GP(400000000U, 200, 0, 1, 0, 12), PLL_FRACN_GP(393216000U, 163, 84, 100, 0, 10), + PLL_FRACN_GP(333333333U, 125, 0, 1, 1, 9), PLL_FRACN_GP(332600000U, 138, 584, 1000, 0, 10), PLL_FRACN_GP(300000000U, 150, 0, 1, 0, 12), PLL_FRACN_GP(241900000U, 201, 584, 1000, 0, 20),