From: Daniel Golle Date: Wed, 25 Jun 2025 23:53:57 +0000 (+0100) Subject: mediatek: mt7988a: 6.12: move SoC dtsi changes to dedicated patch X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=e310d7187ec43e00487659923ce9876bc32c1a04;p=thirdparty%2Fopenwrt.git mediatek: mt7988a: 6.12: move SoC dtsi changes to dedicated patch Move changes to mt7988a.dtsi from patch adding the support for the MT7988A Reference Board to a dedicated patch to ease maintainance. Fixes: f9206d1111 ("kernel/mediatek: 6.12: replace downstream files by patches") Signed-off-by: Daniel Golle --- diff --git a/target/linux/mediatek/patches-6.12/187-arm64-dts-mt7988a-add-serial1-and-serial2-aliases.patch b/target/linux/mediatek/patches-6.12/185-arm64-dts-mt7988a-add-serial1-and-serial2-aliases.patch similarity index 100% rename from target/linux/mediatek/patches-6.12/187-arm64-dts-mt7988a-add-serial1-and-serial2-aliases.patch rename to target/linux/mediatek/patches-6.12/185-arm64-dts-mt7988a-add-serial1-and-serial2-aliases.patch diff --git a/target/linux/mediatek/patches-6.12/186-arm64-dts-mt7988a-complete-dtsi.patch b/target/linux/mediatek/patches-6.12/186-arm64-dts-mt7988a-complete-dtsi.patch new file mode 100644 index 00000000000..b7c609f0f55 --- /dev/null +++ b/target/linux/mediatek/patches-6.12/186-arm64-dts-mt7988a-complete-dtsi.patch @@ -0,0 +1,235 @@ +From: Daniel Golle +Date: Thu, 26 Jun 2025 00:54:32 +0100 +Subject: [PATCH] arm64: dts: mt7988a: complete dtsi + +Work-in-progress patch to complete mt7988a.dtsi +--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +@@ -193,7 +193,7 @@ + }; + + pio: pinctrl@1001f000 { +- compatible = "mediatek,mt7988-pinctrl"; ++ compatible = "mediatek,mt7988-pinctrl", "syscon"; + reg = <0 0x1001f000 0 0x1000>, + <0 0x11c10000 0 0x1000>, + <0 0x11d00000 0 0x1000>, +@@ -212,6 +212,13 @@ + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + ++ snfi_pins: snfi-pins { ++ mux { ++ function = "flash"; ++ groups = "snfi"; ++ }; ++ }; ++ + pcie0_pins: pcie0-pins { + mux { + function = "pcie"; +@@ -278,6 +285,60 @@ + status = "disabled"; + }; + ++ sgmiisys0: syscon@10060000 { ++ compatible = "mediatek,mt7988-sgmiisys", ++ "mediatek,mt7988-sgmiisys0", ++ "syscon", ++ "simple-mfd"; ++ reg = <0 0x10060000 0 0x1000>; ++ resets = <&watchdog 1>; ++ #clock-cells = <1>; ++ ++ sgmiipcs0: pcs { ++ compatible = "mediatek,mt7988-sgmii"; ++ clocks = <&topckgen CLK_TOP_SGM_0_SEL>, ++ <&sgmiisys0 CLK_SGM0_TX_EN>, ++ <&sgmiisys0 CLK_SGM0_RX_EN>; ++ clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx"; ++ #pcs-cells = <0>; ++ }; ++ }; ++ ++ sgmiisys1: syscon@10070000 { ++ compatible = "mediatek,mt7988-sgmiisys", ++ "mediatek,mt7988-sgmiisys1", ++ "syscon", ++ "simple-mfd"; ++ reg = <0 0x10070000 0 0x1000>; ++ resets = <&watchdog 2>; ++ #clock-cells = <1>; ++ ++ sgmiipcs1: pcs { ++ compatible = "mediatek,mt7988-sgmii"; ++ clocks = <&topckgen CLK_TOP_SGM_1_SEL>, ++ <&sgmiisys1 CLK_SGM1_TX_EN>, ++ <&sgmiisys1 CLK_SGM1_RX_EN>; ++ clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx"; ++ #pcs-cells = <0>; ++ }; ++ }; ++ ++ usxgmiisys0: pcs@10080000 { ++ compatible = "mediatek,mt7988-usxgmiisys"; ++ reg = <0 0x10080000 0 0x1000>; ++ resets = <&watchdog 12>; ++ clocks = <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>; ++ #pcs-cells = <0>; ++ }; ++ ++ usxgmiisys1: pcs@10081000 { ++ compatible = "mediatek,mt7988-usxgmiisys"; ++ reg = <0 0x10081000 0 0x1000>; ++ resets = <&watchdog 13>; ++ clocks = <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>; ++ #pcs-cells = <0>; ++ }; ++ + mcusys: mcusys@100e0000 { + compatible = "mediatek,mt7988-mcusys", "syscon"; + reg = <0 0x100e0000 0 0x1000>; +@@ -319,6 +380,32 @@ + status = "disabled"; + }; + ++ snand: spi@11001000 { ++ compatible = "mediatek,mt7986-snand"; ++ reg = <0 0x11001000 0 0x1000>; ++ interrupts = ; ++ clocks = <&infracfg CLK_INFRA_SPINFI>, ++ <&infracfg CLK_INFRA_NFI>, ++ <&infracfg CLK_INFRA_66M_NFI_HCK>; ++ clock-names = "pad_clk", "nfi_clk", "nfi_hclk"; ++ nand-ecc-engine = <&bch>; ++ mediatek,quad-spi; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&snfi_pins>; ++ status = "disabled"; ++ }; ++ ++ bch: ecc@11002000 { ++ compatible = "mediatek,mt7686-ecc"; ++ reg = <0 0x11002000 0 0x1000>; ++ interrupts = ; ++ clocks = <&infracfg CLK_INFRA_NFI>; ++ clock-names = "nfiecc_clk"; ++ status = "disabled"; ++ }; ++ + i2c0: i2c@11003000 { + compatible = "mediatek,mt7981-i2c"; + reg = <0 0x11003000 0 0x1000>, +@@ -425,7 +512,7 @@ + <0 0x0f0f0018 0 0x20>; + }; + +- usb@11190000 { ++ ssusb0: usb@11190000 { + compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci"; + reg = <0 0x11190000 0 0x2e00>, + <0 0x11193e00 0 0x0100>; +@@ -459,6 +546,35 @@ + status = "disabled"; + }; + ++ afe: audio-controller@11210000 { ++ compatible = "mediatek,mt79xx-audio"; ++ reg = <0 0x11210000 0 0x9000>; ++ interrupts = ; ++ clocks = <&infracfg CLK_INFRA_66M_AUD_SLV_BCK>, ++ <&infracfg CLK_INFRA_AUD_26M>, ++ <&infracfg CLK_INFRA_AUD_L>, ++ <&infracfg CLK_INFRA_AUD_AUD>, ++ <&infracfg CLK_INFRA_AUD_EG2>, ++ <&topckgen CLK_TOP_AUD_SEL>, ++ <&topckgen CLK_TOP_AUD_I2S_M>; ++ clock-names = "aud_bus_ck", ++ "aud_26m_ck", ++ "aud_l_ck", ++ "aud_aud_ck", ++ "aud_eg2_ck", ++ "aud_sel", ++ "aud_i2s_m"; ++ assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>, ++ <&topckgen CLK_TOP_A1SYS_SEL>, ++ <&topckgen CLK_TOP_AUD_L_SEL>, ++ <&topckgen CLK_TOP_A_TUNER_SEL>; ++ assigned-clock-parents = <&apmixedsys CLK_APMIXED_APLL2>, ++ <&topckgen CLK_TOP_APLL2_D4>, ++ <&apmixedsys CLK_APMIXED_APLL2>, ++ <&topckgen CLK_TOP_APLL2_D4>; ++ status = "disabled"; ++ }; ++ + mmc0: mmc@11230000 { + compatible = "mediatek,mt7988-mmc"; + reg = <0 0x11230000 0 0x1000>, +@@ -721,6 +837,10 @@ + #address-cells = <1>; + #size-cells = <1>; + ++ cpufreq_calibration: calib@278 { ++ reg = <0x278 0x1>; ++ }; ++ + lvts_calibration: calib@918 { + reg = <0x918 0x28>; + }; +@@ -984,12 +1104,16 @@ + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; ++ pcs-handle = <&sgmiipcs1>, <&usxgmiisys1>; ++ phys = <&xfi_tphy1>; + status = "disabled"; + }; + + gmac2: mac@2 { + compatible = "mediatek,eth-mac"; + reg = <2>; ++ pcs-handle = <&sgmiipcs0>, <&usxgmiisys0>; ++ phys = <&xfi_tphy0>; + status = "disabled"; + }; + +@@ -1002,9 +1126,37 @@ + reg = <15>; + compatible = "ethernet-phy-ieee802.3-c45"; + phy-mode = "internal"; ++ ++ leds { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ i2p5gbe_led0: i2p5gbe-led0@0 { ++ reg = <0>; ++ function = LED_FUNCTION_LAN; ++ status = "disabled"; ++ }; ++ ++ i2p5gbe_led1: i2p5gbe-led1@1 { ++ reg = <1>; ++ function = LED_FUNCTION_LAN; ++ status = "disabled"; ++ }; ++ }; + }; + }; + }; ++ ++ crypto: crypto@15600000 { ++ compatible = "inside-secure,safexcel-eip197b"; ++ reg = <0 0x15600000 0 0x180000>; ++ interrupts = , ++ , ++ , ++ ; ++ interrupt-names = "ring0", "ring1", "ring2", "ring3"; ++ status = "okay"; ++ }; + }; + + thermal-zones { diff --git a/target/linux/mediatek/patches-6.12/188-arm64-dts-mediatek-add-MT7988A-reference-board-devic.patch b/target/linux/mediatek/patches-6.12/188-arm64-dts-mediatek-add-MT7988A-reference-board-devic.patch index 0e0eeb38e17..204a2cb4349 100644 --- a/target/linux/mediatek/patches-6.12/188-arm64-dts-mediatek-add-MT7988A-reference-board-devic.patch +++ b/target/linux/mediatek/patches-6.12/188-arm64-dts-mediatek-add-MT7988A-reference-board-devic.patch @@ -1282,233 +1282,3 @@ Signed-off-by: Daniel Golle +&xsphy { + status = "okay"; +}; ---- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi -@@ -193,7 +193,7 @@ - }; - - pio: pinctrl@1001f000 { -- compatible = "mediatek,mt7988-pinctrl"; -+ compatible = "mediatek,mt7988-pinctrl", "syscon"; - reg = <0 0x1001f000 0 0x1000>, - <0 0x11c10000 0 0x1000>, - <0 0x11d00000 0 0x1000>, -@@ -212,6 +212,13 @@ - interrupt-parent = <&gic>; - #interrupt-cells = <2>; - -+ snfi_pins: snfi-pins { -+ mux { -+ function = "flash"; -+ groups = "snfi"; -+ }; -+ }; -+ - pcie0_pins: pcie0-pins { - mux { - function = "pcie"; -@@ -278,6 +285,60 @@ - status = "disabled"; - }; - -+ sgmiisys0: syscon@10060000 { -+ compatible = "mediatek,mt7988-sgmiisys", -+ "mediatek,mt7988-sgmiisys0", -+ "syscon", -+ "simple-mfd"; -+ reg = <0 0x10060000 0 0x1000>; -+ resets = <&watchdog 1>; -+ #clock-cells = <1>; -+ -+ sgmiipcs0: pcs { -+ compatible = "mediatek,mt7988-sgmii"; -+ clocks = <&topckgen CLK_TOP_SGM_0_SEL>, -+ <&sgmiisys0 CLK_SGM0_TX_EN>, -+ <&sgmiisys0 CLK_SGM0_RX_EN>; -+ clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx"; -+ #pcs-cells = <0>; -+ }; -+ }; -+ -+ sgmiisys1: syscon@10070000 { -+ compatible = "mediatek,mt7988-sgmiisys", -+ "mediatek,mt7988-sgmiisys1", -+ "syscon", -+ "simple-mfd"; -+ reg = <0 0x10070000 0 0x1000>; -+ resets = <&watchdog 2>; -+ #clock-cells = <1>; -+ -+ sgmiipcs1: pcs { -+ compatible = "mediatek,mt7988-sgmii"; -+ clocks = <&topckgen CLK_TOP_SGM_1_SEL>, -+ <&sgmiisys1 CLK_SGM1_TX_EN>, -+ <&sgmiisys1 CLK_SGM1_RX_EN>; -+ clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx"; -+ #pcs-cells = <0>; -+ }; -+ }; -+ -+ usxgmiisys0: pcs@10080000 { -+ compatible = "mediatek,mt7988-usxgmiisys"; -+ reg = <0 0x10080000 0 0x1000>; -+ resets = <&watchdog 12>; -+ clocks = <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>; -+ #pcs-cells = <0>; -+ }; -+ -+ usxgmiisys1: pcs@10081000 { -+ compatible = "mediatek,mt7988-usxgmiisys"; -+ reg = <0 0x10081000 0 0x1000>; -+ resets = <&watchdog 13>; -+ clocks = <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>; -+ #pcs-cells = <0>; -+ }; -+ - mcusys: mcusys@100e0000 { - compatible = "mediatek,mt7988-mcusys", "syscon"; - reg = <0 0x100e0000 0 0x1000>; -@@ -319,6 +380,32 @@ - status = "disabled"; - }; - -+ snand: spi@11001000 { -+ compatible = "mediatek,mt7986-snand"; -+ reg = <0 0x11001000 0 0x1000>; -+ interrupts = ; -+ clocks = <&infracfg CLK_INFRA_SPINFI>, -+ <&infracfg CLK_INFRA_NFI>, -+ <&infracfg CLK_INFRA_66M_NFI_HCK>; -+ clock-names = "pad_clk", "nfi_clk", "nfi_hclk"; -+ nand-ecc-engine = <&bch>; -+ mediatek,quad-spi; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&snfi_pins>; -+ status = "disabled"; -+ }; -+ -+ bch: ecc@11002000 { -+ compatible = "mediatek,mt7686-ecc"; -+ reg = <0 0x11002000 0 0x1000>; -+ interrupts = ; -+ clocks = <&infracfg CLK_INFRA_NFI>; -+ clock-names = "nfiecc_clk"; -+ status = "disabled"; -+ }; -+ - i2c0: i2c@11003000 { - compatible = "mediatek,mt7981-i2c"; - reg = <0 0x11003000 0 0x1000>, -@@ -425,7 +512,7 @@ - <0 0x0f0f0018 0 0x20>; - }; - -- usb@11190000 { -+ ssusb0: usb@11190000 { - compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci"; - reg = <0 0x11190000 0 0x2e00>, - <0 0x11193e00 0 0x0100>; -@@ -459,6 +546,35 @@ - status = "disabled"; - }; - -+ afe: audio-controller@11210000 { -+ compatible = "mediatek,mt79xx-audio"; -+ reg = <0 0x11210000 0 0x9000>; -+ interrupts = ; -+ clocks = <&infracfg CLK_INFRA_66M_AUD_SLV_BCK>, -+ <&infracfg CLK_INFRA_AUD_26M>, -+ <&infracfg CLK_INFRA_AUD_L>, -+ <&infracfg CLK_INFRA_AUD_AUD>, -+ <&infracfg CLK_INFRA_AUD_EG2>, -+ <&topckgen CLK_TOP_AUD_SEL>, -+ <&topckgen CLK_TOP_AUD_I2S_M>; -+ clock-names = "aud_bus_ck", -+ "aud_26m_ck", -+ "aud_l_ck", -+ "aud_aud_ck", -+ "aud_eg2_ck", -+ "aud_sel", -+ "aud_i2s_m"; -+ assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>, -+ <&topckgen CLK_TOP_A1SYS_SEL>, -+ <&topckgen CLK_TOP_AUD_L_SEL>, -+ <&topckgen CLK_TOP_A_TUNER_SEL>; -+ assigned-clock-parents = <&apmixedsys CLK_APMIXED_APLL2>, -+ <&topckgen CLK_TOP_APLL2_D4>, -+ <&apmixedsys CLK_APMIXED_APLL2>, -+ <&topckgen CLK_TOP_APLL2_D4>; -+ status = "disabled"; -+ }; -+ - mmc0: mmc@11230000 { - compatible = "mediatek,mt7988-mmc"; - reg = <0 0x11230000 0 0x1000>, -@@ -721,6 +837,10 @@ - #address-cells = <1>; - #size-cells = <1>; - -+ cpufreq_calibration: calib@278 { -+ reg = <0x278 0x1>; -+ }; -+ - lvts_calibration: calib@918 { - reg = <0x918 0x28>; - }; -@@ -984,12 +1104,16 @@ - gmac1: mac@1 { - compatible = "mediatek,eth-mac"; - reg = <1>; -+ pcs-handle = <&sgmiipcs1>, <&usxgmiisys1>; -+ phys = <&xfi_tphy1>; - status = "disabled"; - }; - - gmac2: mac@2 { - compatible = "mediatek,eth-mac"; - reg = <2>; -+ pcs-handle = <&sgmiipcs0>, <&usxgmiisys0>; -+ phys = <&xfi_tphy0>; - status = "disabled"; - }; - -@@ -1002,9 +1126,37 @@ - reg = <15>; - compatible = "ethernet-phy-ieee802.3-c45"; - phy-mode = "internal"; -+ -+ leds { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ i2p5gbe_led0: i2p5gbe-led0@0 { -+ reg = <0>; -+ function = LED_FUNCTION_LAN; -+ status = "disabled"; -+ }; -+ -+ i2p5gbe_led1: i2p5gbe-led1@1 { -+ reg = <1>; -+ function = LED_FUNCTION_LAN; -+ status = "disabled"; -+ }; -+ }; - }; - }; - }; -+ -+ crypto: crypto@15600000 { -+ compatible = "inside-secure,safexcel-eip197b"; -+ reg = <0 0x15600000 0 0x180000>; -+ interrupts = , -+ , -+ , -+ ; -+ interrupt-names = "ring0", "ring1", "ring2", "ring3"; -+ status = "okay"; -+ }; - }; - - thermal-zones {