From: Alexandru Gagniuc Date: Tue, 13 May 2025 23:45:56 +0000 (-0500) Subject: qualcommbe: v6.12: add upstreamed patches X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=e3478dbd691b54710f26a4b59ab98cceaeb37b51;p=thirdparty%2Fopenwrt.git qualcommbe: v6.12: add upstreamed patches Add relevant patches from upstream, up to v5.16-rc6. The gaps in the patch numbersing are either patches that were picked into the stable kernel (6.12.y), or that are already backported in target/linux/generic. The gaps makes it easy for me to pick these patches from my working kernel git branch. Signed-off-by: Alexandru Gagniuc Link: https://github.com/openwrt/openwrt/pull/18796 Signed-off-by: Robert Marko --- diff --git a/target/linux/qualcommbe/patches-6.12/0002-v6.13-dt-bindings-PCI-qcom-Document-the-IPQ9574-PCIe.patch b/target/linux/qualcommbe/patches-6.12/0002-v6.13-dt-bindings-PCI-qcom-Document-the-IPQ9574-PCIe.patch new file mode 100644 index 00000000000..2c883030e36 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0002-v6.13-dt-bindings-PCI-qcom-Document-the-IPQ9574-PCIe.patch @@ -0,0 +1,101 @@ +From e3ccffe9335ce3bdba93640588fab4560d18485e Mon Sep 17 00:00:00 2001 +From: devi priya +Date: Thu, 1 Aug 2024 11:18:00 +0530 +Subject: [PATCH 02/22] v6.13: dt-bindings: PCI: qcom: Document the IPQ9574 + PCIe controller +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Document the PCIe controller on IPQ9574 platform. + +Link: https://lore.kernel.org/r/20240801054803.3015572-2-quic_srichara@quicinc.com +Signed-off-by: devi priya +Signed-off-by: Sricharan Ramabadhran +Signed-off-by: Krzysztof Wilczyński +Reviewed-by: Krzysztof Kozlowski +Reviewed-by: Manivannan Sadhasivam +--- + .../devicetree/bindings/pci/qcom,pcie.yaml | 50 +++++++++++++++++++ + 1 file changed, 50 insertions(+) + +--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml ++++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +@@ -26,6 +26,7 @@ properties: + - qcom,pcie-ipq8064-v2 + - qcom,pcie-ipq8074 + - qcom,pcie-ipq8074-gen3 ++ - qcom,pcie-ipq9574 + - qcom,pcie-msm8996 + - qcom,pcie-qcs404 + - qcom,pcie-sdm845 +@@ -164,6 +165,7 @@ allOf: + enum: + - qcom,pcie-ipq6018 + - qcom,pcie-ipq8074-gen3 ++ - qcom,pcie-ipq9574 + then: + properties: + reg: +@@ -405,6 +407,53 @@ allOf: + compatible: + contains: + enum: ++ - qcom,pcie-ipq9574 ++ then: ++ properties: ++ clocks: ++ minItems: 6 ++ maxItems: 6 ++ clock-names: ++ items: ++ - const: axi_m # AXI Master clock ++ - const: axi_s # AXI Slave clock ++ - const: axi_bridge ++ - const: rchng ++ - const: ahb ++ - const: aux ++ ++ resets: ++ minItems: 8 ++ maxItems: 8 ++ reset-names: ++ items: ++ - const: pipe # PIPE reset ++ - const: sticky # Core Sticky reset ++ - const: axi_s_sticky # AXI Slave Sticky reset ++ - const: axi_s # AXI Slave reset ++ - const: axi_m_sticky # AXI Master Sticky reset ++ - const: axi_m # AXI Master reset ++ - const: aux # AUX Reset ++ - const: ahb # AHB Reset ++ ++ interrupts: ++ minItems: 8 ++ interrupt-names: ++ items: ++ - const: msi0 ++ - const: msi1 ++ - const: msi2 ++ - const: msi3 ++ - const: msi4 ++ - const: msi5 ++ - const: msi6 ++ - const: msi7 ++ ++ - if: ++ properties: ++ compatible: ++ contains: ++ enum: + - qcom,pcie-qcs404 + then: + properties: +@@ -510,6 +559,7 @@ allOf: + - qcom,pcie-ipq8064v2 + - qcom,pcie-ipq8074 + - qcom,pcie-ipq8074-gen3 ++ - qcom,pcie-ipq9574 + - qcom,pcie-qcs404 + then: + required: diff --git a/target/linux/qualcommbe/patches-6.12/0004-v6.14-arm64-dts-qcom-ipq9574-Add-PCIe-PHYs-and-contr.patch b/target/linux/qualcommbe/patches-6.12/0004-v6.14-arm64-dts-qcom-ipq9574-Add-PCIe-PHYs-and-contr.patch new file mode 100644 index 00000000000..db27e9e6f36 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0004-v6.14-arm64-dts-qcom-ipq9574-Add-PCIe-PHYs-and-contr.patch @@ -0,0 +1,468 @@ +From acb06ebe2d1f043fd597f5c33aff048ae1804293 Mon Sep 17 00:00:00 2001 +From: devi priya +Date: Thu, 1 Aug 2024 11:18:01 +0530 +Subject: [PATCH 04/22] v6.14: arm64: dts: qcom: ipq9574: Add PCIe PHYs and + controller nodes + +Add PCIe0, PCIe1, PCIe2, PCIe3 (and corresponding PHY) devices +found on IPQ9574 platform. The PCIe0 & PCIe1 are 1-lane Gen3 +host whereas PCIe2 & PCIe3 are 2-lane Gen3 host. + +Signed-off-by: devi priya +Signed-off-by: Sricharan Ramabadhran +Link: https://lore.kernel.org/r/20240801054803.3015572-3-quic_srichara@quicinc.com +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq9574.dtsi | 420 +++++++++++++++++++++++++- + 1 file changed, 416 insertions(+), 4 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi +@@ -226,6 +226,52 @@ + reg = <0x00060000 0x6000>; + }; + ++ pcie0_phy: phy@84000 { ++ compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy"; ++ reg = <0x00084000 0x1000>; ++ ++ clocks = <&gcc GCC_PCIE0_AUX_CLK>, ++ <&gcc GCC_PCIE0_AHB_CLK>, ++ <&gcc GCC_PCIE0_PIPE_CLK>; ++ clock-names = "aux", "cfg_ahb", "pipe"; ++ ++ assigned-clocks = <&gcc GCC_PCIE0_AUX_CLK>; ++ assigned-clock-rates = <20000000>; ++ ++ resets = <&gcc GCC_PCIE0_PHY_BCR>, ++ <&gcc GCC_PCIE0PHY_PHY_BCR>; ++ reset-names = "phy", "common"; ++ ++ #clock-cells = <0>; ++ clock-output-names = "gcc_pcie0_pipe_clk_src"; ++ ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ pcie2_phy: phy@8c000 { ++ compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy"; ++ reg = <0x0008c000 0x2000>; ++ ++ clocks = <&gcc GCC_PCIE2_AUX_CLK>, ++ <&gcc GCC_PCIE2_AHB_CLK>, ++ <&gcc GCC_PCIE2_PIPE_CLK>; ++ clock-names = "aux", "cfg_ahb", "pipe"; ++ ++ assigned-clocks = <&gcc GCC_PCIE2_AUX_CLK>; ++ assigned-clock-rates = <20000000>; ++ ++ resets = <&gcc GCC_PCIE2_PHY_BCR>, ++ <&gcc GCC_PCIE2PHY_PHY_BCR>; ++ reset-names = "phy", "common"; ++ ++ #clock-cells = <0>; ++ clock-output-names = "gcc_pcie2_pipe_clk_src"; ++ ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ + rng: rng@e3000 { + compatible = "qcom,prng-ee"; + reg = <0x000e3000 0x1000>; +@@ -243,6 +289,52 @@ + status = "disabled"; + }; + ++ pcie3_phy: phy@f4000 { ++ compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy"; ++ reg = <0x000f4000 0x2000>; ++ ++ clocks = <&gcc GCC_PCIE3_AUX_CLK>, ++ <&gcc GCC_PCIE3_AHB_CLK>, ++ <&gcc GCC_PCIE3_PIPE_CLK>; ++ clock-names = "aux", "cfg_ahb", "pipe"; ++ ++ assigned-clocks = <&gcc GCC_PCIE3_AUX_CLK>; ++ assigned-clock-rates = <20000000>; ++ ++ resets = <&gcc GCC_PCIE3_PHY_BCR>, ++ <&gcc GCC_PCIE3PHY_PHY_BCR>; ++ reset-names = "phy", "common"; ++ ++ #clock-cells = <0>; ++ clock-output-names = "gcc_pcie3_pipe_clk_src"; ++ ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ pcie1_phy: phy@fc000 { ++ compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy"; ++ reg = <0x000fc000 0x1000>; ++ ++ clocks = <&gcc GCC_PCIE1_AUX_CLK>, ++ <&gcc GCC_PCIE1_AHB_CLK>, ++ <&gcc GCC_PCIE1_PIPE_CLK>; ++ clock-names = "aux", "cfg_ahb", "pipe"; ++ ++ assigned-clocks = <&gcc GCC_PCIE1_AUX_CLK>; ++ assigned-clock-rates = <20000000>; ++ ++ resets = <&gcc GCC_PCIE1_PHY_BCR>, ++ <&gcc GCC_PCIE1PHY_PHY_BCR>; ++ reset-names = "phy", "common"; ++ ++ #clock-cells = <0>; ++ clock-output-names = "gcc_pcie1_pipe_clk_src"; ++ ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ + qfprom: efuse@a4000 { + compatible = "qcom,ipq9574-qfprom", "qcom,qfprom"; + reg = <0x000a4000 0x5a1>; +@@ -309,10 +401,10 @@ + clocks = <&xo_board_clk>, + <&sleep_clk>, + <0>, +- <0>, +- <0>, +- <0>, +- <0>, ++ <&pcie0_phy>, ++ <&pcie1_phy>, ++ <&pcie2_phy>, ++ <&pcie3_phy>, + <0>; + #clock-cells = <1>; + #reset-cells = <1>; +@@ -756,6 +848,326 @@ + status = "disabled"; + }; + }; ++ ++ pcie1: pcie@10000000 { ++ compatible = "qcom,pcie-ipq9574"; ++ reg = <0x10000000 0xf1d>, ++ <0x10000f20 0xa8>, ++ <0x10001000 0x1000>, ++ <0x000f8000 0x4000>, ++ <0x10100000 0x1000>; ++ reg-names = "dbi", "elbi", "atu", "parf", "config"; ++ device_type = "pci"; ++ linux,pci-domain = <1>; ++ bus-range = <0x00 0xff>; ++ num-lanes = <1>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ ranges = <0x01000000 0x0 0x00000000 0x10200000 0x0 0x100000>, ++ <0x02000000 0x0 0x10300000 0x10300000 0x0 0x7d00000>; ++ ++ interrupts = , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ interrupt-names = "msi0", ++ "msi1", ++ "msi2", ++ "msi3", ++ "msi4", ++ "msi5", ++ "msi6", ++ "msi7"; ++ ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0x7>; ++ interrupt-map = <0 0 0 1 &intc 0 0 35 IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 2 &intc 0 0 49 IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 3 &intc 0 0 84 IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 4 &intc 0 0 85 IRQ_TYPE_LEVEL_HIGH>; ++ ++ clocks = <&gcc GCC_PCIE1_AXI_M_CLK>, ++ <&gcc GCC_PCIE1_AXI_S_CLK>, ++ <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>, ++ <&gcc GCC_PCIE1_RCHNG_CLK>, ++ <&gcc GCC_PCIE1_AHB_CLK>, ++ <&gcc GCC_PCIE1_AUX_CLK>; ++ clock-names = "axi_m", ++ "axi_s", ++ "axi_bridge", ++ "rchng", ++ "ahb", ++ "aux"; ++ ++ resets = <&gcc GCC_PCIE1_PIPE_ARES>, ++ <&gcc GCC_PCIE1_CORE_STICKY_ARES>, ++ <&gcc GCC_PCIE1_AXI_S_STICKY_ARES>, ++ <&gcc GCC_PCIE1_AXI_S_ARES>, ++ <&gcc GCC_PCIE1_AXI_M_STICKY_ARES>, ++ <&gcc GCC_PCIE1_AXI_M_ARES>, ++ <&gcc GCC_PCIE1_AUX_ARES>, ++ <&gcc GCC_PCIE1_AHB_ARES>; ++ reset-names = "pipe", ++ "sticky", ++ "axi_s_sticky", ++ "axi_s", ++ "axi_m_sticky", ++ "axi_m", ++ "aux", ++ "ahb"; ++ ++ phys = <&pcie1_phy>; ++ phy-names = "pciephy"; ++ interconnects = <&gcc MASTER_ANOC_PCIE1 &gcc SLAVE_ANOC_PCIE1>, ++ <&gcc MASTER_SNOC_PCIE1 &gcc SLAVE_SNOC_PCIE1>; ++ interconnect-names = "pcie-mem", "cpu-pcie"; ++ status = "disabled"; ++ }; ++ ++ pcie3: pcie@18000000 { ++ compatible = "qcom,pcie-ipq9574"; ++ reg = <0x18000000 0xf1d>, ++ <0x18000f20 0xa8>, ++ <0x18001000 0x1000>, ++ <0x000f0000 0x4000>, ++ <0x18100000 0x1000>; ++ reg-names = "dbi", "elbi", "atu", "parf", "config"; ++ device_type = "pci"; ++ linux,pci-domain = <3>; ++ bus-range = <0x00 0xff>; ++ num-lanes = <2>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ ranges = <0x01000000 0x0 0x00000000 0x18200000 0x0 0x100000>, ++ <0x02000000 0x0 0x18300000 0x18300000 0x0 0x7d00000>; ++ ++ interrupts = , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ interrupt-names = "msi0", ++ "msi1", ++ "msi2", ++ "msi3", ++ "msi4", ++ "msi5", ++ "msi6", ++ "msi7"; ++ ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0x7>; ++ interrupt-map = <0 0 0 1 &intc 0 0 189 IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 2 &intc 0 0 190 IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 3 &intc 0 0 191 IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 4 &intc 0 0 192 IRQ_TYPE_LEVEL_HIGH>; ++ ++ clocks = <&gcc GCC_PCIE3_AXI_M_CLK>, ++ <&gcc GCC_PCIE3_AXI_S_CLK>, ++ <&gcc GCC_PCIE3_AXI_S_BRIDGE_CLK>, ++ <&gcc GCC_PCIE3_RCHNG_CLK>, ++ <&gcc GCC_PCIE3_AHB_CLK>, ++ <&gcc GCC_PCIE3_AUX_CLK>; ++ clock-names = "axi_m", ++ "axi_s", ++ "axi_bridge", ++ "rchng", ++ "ahb", ++ "aux"; ++ ++ resets = <&gcc GCC_PCIE3_PIPE_ARES>, ++ <&gcc GCC_PCIE3_CORE_STICKY_ARES>, ++ <&gcc GCC_PCIE3_AXI_S_STICKY_ARES>, ++ <&gcc GCC_PCIE3_AXI_S_ARES>, ++ <&gcc GCC_PCIE3_AXI_M_STICKY_ARES>, ++ <&gcc GCC_PCIE3_AXI_M_ARES>, ++ <&gcc GCC_PCIE3_AUX_ARES>, ++ <&gcc GCC_PCIE3_AHB_ARES>; ++ reset-names = "pipe", ++ "sticky", ++ "axi_s_sticky", ++ "axi_s", ++ "axi_m_sticky", ++ "axi_m", ++ "aux", ++ "ahb"; ++ ++ phys = <&pcie3_phy>; ++ phy-names = "pciephy"; ++ interconnects = <&gcc MASTER_ANOC_PCIE3 &gcc SLAVE_ANOC_PCIE3>, ++ <&gcc MASTER_SNOC_PCIE3 &gcc SLAVE_SNOC_PCIE3>; ++ interconnect-names = "pcie-mem", "cpu-pcie"; ++ status = "disabled"; ++ }; ++ ++ pcie2: pcie@20000000 { ++ compatible = "qcom,pcie-ipq9574"; ++ reg = <0x20000000 0xf1d>, ++ <0x20000f20 0xa8>, ++ <0x20001000 0x1000>, ++ <0x00088000 0x4000>, ++ <0x20100000 0x1000>; ++ reg-names = "dbi", "elbi", "atu", "parf", "config"; ++ device_type = "pci"; ++ linux,pci-domain = <2>; ++ bus-range = <0x00 0xff>; ++ num-lanes = <2>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ ranges = <0x01000000 0x0 0x00000000 0x20200000 0x0 0x100000>, ++ <0x02000000 0x0 0x20300000 0x20300000 0x0 0x7d00000>; ++ ++ interrupts = , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ interrupt-names = "msi0", ++ "msi1", ++ "msi2", ++ "msi3", ++ "msi4", ++ "msi5", ++ "msi6", ++ "msi7"; ++ ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0x7>; ++ interrupt-map = <0 0 0 1 &intc 0 0 164 IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 2 &intc 0 0 165 IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 3 &intc 0 0 186 IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 4 &intc 0 0 187 IRQ_TYPE_LEVEL_HIGH>; ++ ++ clocks = <&gcc GCC_PCIE2_AXI_M_CLK>, ++ <&gcc GCC_PCIE2_AXI_S_CLK>, ++ <&gcc GCC_PCIE2_AXI_S_BRIDGE_CLK>, ++ <&gcc GCC_PCIE2_RCHNG_CLK>, ++ <&gcc GCC_PCIE2_AHB_CLK>, ++ <&gcc GCC_PCIE2_AUX_CLK>; ++ clock-names = "axi_m", ++ "axi_s", ++ "axi_bridge", ++ "rchng", ++ "ahb", ++ "aux"; ++ ++ resets = <&gcc GCC_PCIE2_PIPE_ARES>, ++ <&gcc GCC_PCIE2_CORE_STICKY_ARES>, ++ <&gcc GCC_PCIE2_AXI_S_STICKY_ARES>, ++ <&gcc GCC_PCIE2_AXI_S_ARES>, ++ <&gcc GCC_PCIE2_AXI_M_STICKY_ARES>, ++ <&gcc GCC_PCIE2_AXI_M_ARES>, ++ <&gcc GCC_PCIE2_AUX_ARES>, ++ <&gcc GCC_PCIE2_AHB_ARES>; ++ reset-names = "pipe", ++ "sticky", ++ "axi_s_sticky", ++ "axi_s", ++ "axi_m_sticky", ++ "axi_m", ++ "aux", ++ "ahb"; ++ ++ phys = <&pcie2_phy>; ++ phy-names = "pciephy"; ++ interconnects = <&gcc MASTER_ANOC_PCIE2 &gcc SLAVE_ANOC_PCIE2>, ++ <&gcc MASTER_SNOC_PCIE2 &gcc SLAVE_SNOC_PCIE2>; ++ interconnect-names = "pcie-mem", "cpu-pcie"; ++ status = "disabled"; ++ }; ++ ++ pcie0: pci@28000000 { ++ compatible = "qcom,pcie-ipq9574"; ++ reg = <0x28000000 0xf1d>, ++ <0x28000f20 0xa8>, ++ <0x28001000 0x1000>, ++ <0x00080000 0x4000>, ++ <0x28100000 0x1000>; ++ reg-names = "dbi", "elbi", "atu", "parf", "config"; ++ device_type = "pci"; ++ linux,pci-domain = <0>; ++ bus-range = <0x00 0xff>; ++ num-lanes = <1>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ ranges = <0x01000000 0x0 0x00000000 0x28200000 0x0 0x100000>, ++ <0x02000000 0x0 0x28300000 0x28300000 0x0 0x7d00000>; ++ interrupts = , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ interrupt-names = "msi0", ++ "msi1", ++ "msi2", ++ "msi3", ++ "msi4", ++ "msi5", ++ "msi6", ++ "msi7"; ++ ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0x7>; ++ interrupt-map = <0 0 0 1 &intc 0 0 75 IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 2 &intc 0 0 78 IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 3 &intc 0 0 79 IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 4 &intc 0 0 83 IRQ_TYPE_LEVEL_HIGH>; ++ ++ clocks = <&gcc GCC_PCIE0_AXI_M_CLK>, ++ <&gcc GCC_PCIE0_AXI_S_CLK>, ++ <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, ++ <&gcc GCC_PCIE0_RCHNG_CLK>, ++ <&gcc GCC_PCIE0_AHB_CLK>, ++ <&gcc GCC_PCIE0_AUX_CLK>; ++ clock-names = "axi_m", ++ "axi_s", ++ "axi_bridge", ++ "rchng", ++ "ahb", ++ "aux"; ++ ++ resets = <&gcc GCC_PCIE0_PIPE_ARES>, ++ <&gcc GCC_PCIE0_CORE_STICKY_ARES>, ++ <&gcc GCC_PCIE0_AXI_S_STICKY_ARES>, ++ <&gcc GCC_PCIE0_AXI_S_ARES>, ++ <&gcc GCC_PCIE0_AXI_M_STICKY_ARES>, ++ <&gcc GCC_PCIE0_AXI_M_ARES>, ++ <&gcc GCC_PCIE0_AUX_ARES>, ++ <&gcc GCC_PCIE0_AHB_ARES>; ++ reset-names = "pipe", ++ "sticky", ++ "axi_s_sticky", ++ "axi_s", ++ "axi_m_sticky", ++ "axi_m", ++ "aux", ++ "ahb"; ++ ++ phys = <&pcie0_phy>; ++ phy-names = "pciephy"; ++ interconnects = <&gcc MASTER_ANOC_PCIE0 &gcc SLAVE_ANOC_PCIE0>, ++ <&gcc MASTER_SNOC_PCIE0 &gcc SLAVE_SNOC_PCIE0>; ++ interconnect-names = "pcie-mem", "cpu-pcie"; ++ status = "disabled"; ++ }; ++ + }; + + thermal-zones { diff --git a/target/linux/qualcommbe/patches-6.12/0005-v6.14-arm64-dts-qcom-ipq9574-Enable-PCIe-PHYs-and-co.patch b/target/linux/qualcommbe/patches-6.12/0005-v6.14-arm64-dts-qcom-ipq9574-Enable-PCIe-PHYs-and-co.patch new file mode 100644 index 00000000000..f07e422966f --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0005-v6.14-arm64-dts-qcom-ipq9574-Enable-PCIe-PHYs-and-co.patch @@ -0,0 +1,152 @@ +From 695cb0b8f9c525fe6d3ffbc349bc6087acd71201 Mon Sep 17 00:00:00 2001 +From: devi priya +Date: Thu, 1 Aug 2024 11:18:02 +0530 +Subject: [PATCH 05/22] v6.14: arm64: dts: qcom: ipq9574: Enable PCIe PHYs and + controllers + +Enable the PCIe controller and PHY nodes corresponding to RDP 433. + +Signed-off-by: devi priya +Signed-off-by: Sricharan Ramabadhran +Link: https://lore.kernel.org/r/20240801054803.3015572-4-quic_srichara@quicinc.com +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 113 ++++++++++++++++++++ + 1 file changed, 113 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts ++++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +@@ -8,6 +8,7 @@ + + /dts-v1/; + ++#include + #include "ipq9574-rdp-common.dtsi" + + / { +@@ -15,6 +16,45 @@ + compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574"; + }; + ++&pcie1_phy { ++ status = "okay"; ++}; ++ ++&pcie1 { ++ pinctrl-0 = <&pcie1_default>; ++ pinctrl-names = "default"; ++ ++ perst-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>; ++ wake-gpios = <&tlmm 27 GPIO_ACTIVE_LOW>; ++ status = "okay"; ++}; ++ ++&pcie2_phy { ++ status = "okay"; ++}; ++ ++&pcie2 { ++ pinctrl-0 = <&pcie2_default>; ++ pinctrl-names = "default"; ++ ++ perst-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>; ++ wake-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>; ++ status = "okay"; ++}; ++ ++&pcie3_phy { ++ status = "okay"; ++}; ++ ++&pcie3 { ++ pinctrl-0 = <&pcie3_default>; ++ pinctrl-names = "default"; ++ ++ perst-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>; ++ wake-gpios = <&tlmm 33 GPIO_ACTIVE_LOW>; ++ status = "okay"; ++}; ++ + &sdhc_1 { + pinctrl-0 = <&sdc_default_state>; + pinctrl-names = "default"; +@@ -28,6 +68,79 @@ + }; + + &tlmm { ++ ++ pcie1_default: pcie1-default-state { ++ clkreq-n-pins { ++ pins = "gpio25"; ++ function = "pcie1_clk"; ++ drive-strength = <6>; ++ bias-pull-up; ++ }; ++ ++ perst-n-pins { ++ pins = "gpio26"; ++ function = "gpio"; ++ drive-strength = <8>; ++ bias-pull-down; ++ output-low; ++ }; ++ ++ wake-n-pins { ++ pins = "gpio27"; ++ function = "pcie1_wake"; ++ drive-strength = <6>; ++ bias-pull-up; ++ }; ++ }; ++ ++ pcie2_default: pcie2-default-state { ++ clkreq-n-pins { ++ pins = "gpio28"; ++ function = "pcie2_clk"; ++ drive-strength = <6>; ++ bias-pull-up; ++ }; ++ ++ perst-n-pins { ++ pins = "gpio29"; ++ function = "gpio"; ++ drive-strength = <8>; ++ bias-pull-down; ++ output-low; ++ }; ++ ++ wake-n-pins { ++ pins = "gpio30"; ++ function = "pcie2_wake"; ++ drive-strength = <6>; ++ bias-pull-up; ++ }; ++ }; ++ ++ pcie3_default: pcie3-default-state { ++ clkreq-n-pins { ++ pins = "gpio31"; ++ function = "pcie3_clk"; ++ drive-strength = <6>; ++ bias-pull-up; ++ }; ++ ++ perst-n-pins { ++ pins = "gpio32"; ++ function = "gpio"; ++ drive-strength = <8>; ++ bias-pull-up; ++ output-low; ++ }; ++ ++ wake-n-pins { ++ pins = "gpio33"; ++ function = "pcie3_wake"; ++ drive-strength = <6>; ++ bias-pull-up; ++ }; ++ }; ++ + sdc_default_state: sdc-default-state { + clk-pins { + pins = "gpio5"; diff --git a/target/linux/qualcommbe/patches-6.12/0006-v6.14-dt-bindings-clock-qcom-Add-CMN-PLL-clock-contr.patch b/target/linux/qualcommbe/patches-6.12/0006-v6.14-dt-bindings-clock-qcom-Add-CMN-PLL-clock-contr.patch new file mode 100644 index 00000000000..f0087764a17 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0006-v6.14-dt-bindings-clock-qcom-Add-CMN-PLL-clock-contr.patch @@ -0,0 +1,132 @@ +From f4b785b3360c594bb10bd6f1dc5096b3e93f86d9 Mon Sep 17 00:00:00 2001 +From: Luo Jie +Date: Fri, 3 Jan 2025 15:31:34 +0800 +Subject: [PATCH 06/22] v6.14: dt-bindings: clock: qcom: Add CMN PLL clock + controller for IPQ SoC + +The CMN PLL controller provides clocks to networking hardware blocks +and to GCC on Qualcomm IPQ9574 SoC. It receives input clock from the +on-chip Wi-Fi, and produces output clocks at fixed rates. These output +rates are predetermined, and are unrelated to the input clock rate. +The primary purpose of CMN PLL is to supply clocks to the networking +hardware such as PPE (packet process engine), PCS and the externally +connected switch or PHY device. The CMN PLL block also outputs fixed +rate clocks to GCC, such as 24 MHZ as XO clock and 32 KHZ as sleep +clock supplied to GCC. + +Signed-off-by: Luo Jie +Reviewed-by: Krzysztof Kozlowski +Link: https://lore.kernel.org/r/20250103-qcom_ipq_cmnpll-v8-1-c89fb4d4849d@quicinc.com +Signed-off-by: Bjorn Andersson +--- + .../bindings/clock/qcom,ipq9574-cmn-pll.yaml | 77 +++++++++++++++++++ + include/dt-bindings/clock/qcom,ipq-cmn-pll.h | 22 ++++++ + 2 files changed, 99 insertions(+) + create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml + create mode 100644 include/dt-bindings/clock/qcom,ipq-cmn-pll.h + +--- /dev/null ++++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml +@@ -0,0 +1,77 @@ ++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Qualcomm CMN PLL Clock Controller on IPQ SoC ++ ++maintainers: ++ - Bjorn Andersson ++ - Luo Jie ++ ++description: ++ The CMN (or common) PLL clock controller expects a reference ++ input clock. This reference clock is from the on-board Wi-Fi. ++ The CMN PLL supplies a number of fixed rate output clocks to ++ the devices providing networking functions and to GCC. These ++ networking hardware include PPE (packet process engine), PCS ++ and the externally connected switch or PHY devices. The CMN ++ PLL block also outputs fixed rate clocks to GCC. The PLL's ++ primary function is to enable fixed rate output clocks for ++ networking hardware functions used with the IPQ SoC. ++ ++properties: ++ compatible: ++ enum: ++ - qcom,ipq9574-cmn-pll ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ items: ++ - description: The reference clock. The supported clock rates include ++ 25000000, 31250000, 40000000, 48000000, 50000000 and 96000000 HZ. ++ - description: The AHB clock ++ - description: The SYS clock ++ description: ++ The reference clock is the source clock of CMN PLL, which is from the ++ Wi-Fi. The AHB and SYS clocks must be enabled to access CMN PLL ++ clock registers. ++ ++ clock-names: ++ items: ++ - const: ref ++ - const: ahb ++ - const: sys ++ ++ "#clock-cells": ++ const: 1 ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - clock-names ++ - "#clock-cells" ++ ++additionalProperties: false ++ ++examples: ++ - | ++ #include ++ #include ++ ++ cmn_pll: clock-controller@9b000 { ++ compatible = "qcom,ipq9574-cmn-pll"; ++ reg = <0x0009b000 0x800>; ++ clocks = <&cmn_pll_ref_clk>, ++ <&gcc GCC_CMN_12GPLL_AHB_CLK>, ++ <&gcc GCC_CMN_12GPLL_SYS_CLK>; ++ clock-names = "ref", "ahb", "sys"; ++ #clock-cells = <1>; ++ assigned-clocks = <&cmn_pll CMN_PLL_CLK>; ++ assigned-clock-rates-u64 = /bits/ 64 <12000000000>; ++ }; ++... +--- /dev/null ++++ b/include/dt-bindings/clock/qcom,ipq-cmn-pll.h +@@ -0,0 +1,22 @@ ++/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ ++/* ++ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. ++ */ ++ ++#ifndef _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H ++#define _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H ++ ++/* CMN PLL core clock. */ ++#define CMN_PLL_CLK 0 ++ ++/* The output clocks from CMN PLL of IPQ9574. */ ++#define XO_24MHZ_CLK 1 ++#define SLEEP_32KHZ_CLK 2 ++#define PCS_31P25MHZ_CLK 3 ++#define NSS_1200MHZ_CLK 4 ++#define PPE_353MHZ_CLK 5 ++#define ETH0_50MHZ_CLK 6 ++#define ETH1_50MHZ_CLK 7 ++#define ETH2_50MHZ_CLK 8 ++#define ETH_25MHZ_CLK 9 ++#endif diff --git a/target/linux/qualcommbe/patches-6.12/0007-v6.14-clk-qcom-Add-CMN-PLL-clock-controller-driver-f.patch b/target/linux/qualcommbe/patches-6.12/0007-v6.14-clk-qcom-Add-CMN-PLL-clock-controller-driver-f.patch new file mode 100644 index 00000000000..edbbf8e13dc --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0007-v6.14-clk-qcom-Add-CMN-PLL-clock-controller-driver-f.patch @@ -0,0 +1,501 @@ +From 51c937f5d7a3b239b637555bbd4dc0017b5cccba Mon Sep 17 00:00:00 2001 +From: Luo Jie +Date: Fri, 3 Jan 2025 15:31:35 +0800 +Subject: [PATCH 07/22] v6.14: clk: qcom: Add CMN PLL clock controller driver + for IPQ SoC + +The CMN PLL clock controller supplies clocks to the hardware +blocks that together make up the Ethernet function on Qualcomm +IPQ SoCs and to GCC. The driver is initially supported for +IPQ9574 SoC. + +The CMN PLL clock controller expects a reference input clock +from the on-board Wi-Fi block acting as clock source. The input +reference clock needs to be configured to one of the supported +clock rates. + +The controller supplies a number of fixed-rate output clocks. +For the IPQ9574, there is one output clock of 353 MHZ to PPE +(Packet Process Engine) hardware block, three 50 MHZ output +clocks and an additional 25 MHZ output clock supplied to the +connected Ethernet devices. The PLL also supplies a 24 MHZ +clock as XO and a 32 KHZ sleep clock to GCC, and one 31.25 +MHZ clock to PCS. + +Signed-off-by: Luo Jie +Acked-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20250103-qcom_ipq_cmnpll-v8-2-c89fb4d4849d@quicinc.com +Signed-off-by: Bjorn Andersson +--- + drivers/clk/qcom/Kconfig | 9 + + drivers/clk/qcom/Makefile | 1 + + drivers/clk/qcom/ipq-cmn-pll.c | 435 +++++++++++++++++++++++++++++++++ + 3 files changed, 445 insertions(+) + create mode 100644 drivers/clk/qcom/ipq-cmn-pll.c + +--- a/drivers/clk/qcom/Kconfig ++++ b/drivers/clk/qcom/Kconfig +@@ -190,6 +190,15 @@ config IPQ_APSS_6018 + Say Y if you want to support CPU frequency scaling on + ipq based devices. + ++config IPQ_CMN_PLL ++ tristate "IPQ CMN PLL Clock Controller" ++ help ++ Support for CMN PLL clock controller on IPQ platform. The ++ CMN PLL consumes the AHB/SYS clocks from GCC and supplies ++ the output clocks to the networking hardware and GCC blocks. ++ Say Y or M if you want to support CMN PLL clock on the IPQ ++ based devices. ++ + config IPQ_GCC_4019 + tristate "IPQ4019 Global Clock Controller" + help +--- a/drivers/clk/qcom/Makefile ++++ b/drivers/clk/qcom/Makefile +@@ -29,6 +29,7 @@ obj-$(CONFIG_CLK_X1E80100_TCSRCC) += tcs + obj-$(CONFIG_CLK_QCM2290_GPUCC) += gpucc-qcm2290.o + obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o + obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o ++obj-$(CONFIG_IPQ_CMN_PLL) += ipq-cmn-pll.o + obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o + obj-$(CONFIG_IPQ_GCC_5018) += gcc-ipq5018.o + obj-$(CONFIG_IPQ_GCC_5332) += gcc-ipq5332.o +--- /dev/null ++++ b/drivers/clk/qcom/ipq-cmn-pll.c +@@ -0,0 +1,435 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. ++ */ ++ ++/* ++ * CMN PLL block expects the reference clock from on-board Wi-Fi block, ++ * and supplies fixed rate clocks as output to the networking hardware ++ * blocks and to GCC. The networking related blocks include PPE (packet ++ * process engine), the externally connected PHY or switch devices, and ++ * the PCS. ++ * ++ * On the IPQ9574 SoC, there are three clocks with 50 MHZ and one clock ++ * with 25 MHZ which are output from the CMN PLL to Ethernet PHY (or switch), ++ * and one clock with 353 MHZ to PPE. The other fixed rate output clocks ++ * are supplied to GCC (24 MHZ as XO and 32 KHZ as sleep clock), and to PCS ++ * with 31.25 MHZ. ++ * ++ * +---------+ ++ * | GCC | ++ * +--+---+--+ ++ * AHB CLK| |SYS CLK ++ * V V ++ * +-------+---+------+ ++ * | +-------------> eth0-50mhz ++ * REF CLK | IPQ9574 | ++ * -------->+ +-------------> eth1-50mhz ++ * | CMN PLL block | ++ * | +-------------> eth2-50mhz ++ * | | ++ * +----+----+----+---+-------------> eth-25mhz ++ * | | | ++ * V V V ++ * GCC PCS NSS/PPE ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#define CMN_PLL_REFCLK_SRC_SELECTION 0x28 ++#define CMN_PLL_REFCLK_SRC_DIV GENMASK(9, 8) ++ ++#define CMN_PLL_LOCKED 0x64 ++#define CMN_PLL_CLKS_LOCKED BIT(8) ++ ++#define CMN_PLL_POWER_ON_AND_RESET 0x780 ++#define CMN_ANA_EN_SW_RSTN BIT(6) ++ ++#define CMN_PLL_REFCLK_CONFIG 0x784 ++#define CMN_PLL_REFCLK_EXTERNAL BIT(9) ++#define CMN_PLL_REFCLK_DIV GENMASK(8, 4) ++#define CMN_PLL_REFCLK_INDEX GENMASK(3, 0) ++ ++#define CMN_PLL_CTRL 0x78c ++#define CMN_PLL_CTRL_LOCK_DETECT_EN BIT(15) ++ ++#define CMN_PLL_DIVIDER_CTRL 0x794 ++#define CMN_PLL_DIVIDER_CTRL_FACTOR GENMASK(9, 0) ++ ++/** ++ * struct cmn_pll_fixed_output_clk - CMN PLL output clocks information ++ * @id: Clock specifier to be supplied ++ * @name: Clock name to be registered ++ * @rate: Clock rate ++ */ ++struct cmn_pll_fixed_output_clk { ++ unsigned int id; ++ const char *name; ++ unsigned long rate; ++}; ++ ++/** ++ * struct clk_cmn_pll - CMN PLL hardware specific data ++ * @regmap: hardware regmap. ++ * @hw: handle between common and hardware-specific interfaces ++ */ ++struct clk_cmn_pll { ++ struct regmap *regmap; ++ struct clk_hw hw; ++}; ++ ++#define CLK_PLL_OUTPUT(_id, _name, _rate) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .rate = _rate, \ ++} ++ ++#define to_clk_cmn_pll(_hw) container_of(_hw, struct clk_cmn_pll, hw) ++ ++static const struct regmap_config ipq_cmn_pll_regmap_config = { ++ .reg_bits = 32, ++ .reg_stride = 4, ++ .val_bits = 32, ++ .max_register = 0x7fc, ++ .fast_io = true, ++}; ++ ++static const struct cmn_pll_fixed_output_clk ipq9574_output_clks[] = { ++ CLK_PLL_OUTPUT(XO_24MHZ_CLK, "xo-24mhz", 24000000UL), ++ CLK_PLL_OUTPUT(SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL), ++ CLK_PLL_OUTPUT(PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL), ++ CLK_PLL_OUTPUT(NSS_1200MHZ_CLK, "nss-1200mhz", 1200000000UL), ++ CLK_PLL_OUTPUT(PPE_353MHZ_CLK, "ppe-353mhz", 353000000UL), ++ CLK_PLL_OUTPUT(ETH0_50MHZ_CLK, "eth0-50mhz", 50000000UL), ++ CLK_PLL_OUTPUT(ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL), ++ CLK_PLL_OUTPUT(ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL), ++ CLK_PLL_OUTPUT(ETH_25MHZ_CLK, "eth-25mhz", 25000000UL), ++}; ++ ++/* ++ * CMN PLL has the single parent clock, which supports the several ++ * possible parent clock rates, each parent clock rate is reflected ++ * by the specific reference index value in the hardware. ++ */ ++static int ipq_cmn_pll_find_freq_index(unsigned long parent_rate) ++{ ++ int index = -EINVAL; ++ ++ switch (parent_rate) { ++ case 25000000: ++ index = 3; ++ break; ++ case 31250000: ++ index = 4; ++ break; ++ case 40000000: ++ index = 6; ++ break; ++ case 48000000: ++ case 96000000: ++ /* ++ * Parent clock rate 48 MHZ and 96 MHZ take the same value ++ * of reference clock index. 96 MHZ needs the source clock ++ * divider to be programmed as 2. ++ */ ++ index = 7; ++ break; ++ case 50000000: ++ index = 8; ++ break; ++ default: ++ break; ++ } ++ ++ return index; ++} ++ ++static unsigned long clk_cmn_pll_recalc_rate(struct clk_hw *hw, ++ unsigned long parent_rate) ++{ ++ struct clk_cmn_pll *cmn_pll = to_clk_cmn_pll(hw); ++ u32 val, factor; ++ ++ /* ++ * The value of CMN_PLL_DIVIDER_CTRL_FACTOR is automatically adjusted ++ * by HW according to the parent clock rate. ++ */ ++ regmap_read(cmn_pll->regmap, CMN_PLL_DIVIDER_CTRL, &val); ++ factor = FIELD_GET(CMN_PLL_DIVIDER_CTRL_FACTOR, val); ++ ++ return parent_rate * 2 * factor; ++} ++ ++static int clk_cmn_pll_determine_rate(struct clk_hw *hw, ++ struct clk_rate_request *req) ++{ ++ int ret; ++ ++ /* Validate the rate of the single parent clock. */ ++ ret = ipq_cmn_pll_find_freq_index(req->best_parent_rate); ++ ++ return ret < 0 ? ret : 0; ++} ++ ++/* ++ * This function is used to initialize the CMN PLL to enable the fixed ++ * rate output clocks. It is expected to be configured once. ++ */ ++static int clk_cmn_pll_set_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long parent_rate) ++{ ++ struct clk_cmn_pll *cmn_pll = to_clk_cmn_pll(hw); ++ int ret, index; ++ u32 val; ++ ++ /* ++ * Configure the reference input clock selection as per the given ++ * parent clock. The output clock rates are always of fixed value. ++ */ ++ index = ipq_cmn_pll_find_freq_index(parent_rate); ++ if (index < 0) ++ return index; ++ ++ ret = regmap_update_bits(cmn_pll->regmap, CMN_PLL_REFCLK_CONFIG, ++ CMN_PLL_REFCLK_INDEX, ++ FIELD_PREP(CMN_PLL_REFCLK_INDEX, index)); ++ if (ret) ++ return ret; ++ ++ /* ++ * Update the source clock rate selection and source clock ++ * divider as 2 when the parent clock rate is 96 MHZ. ++ */ ++ if (parent_rate == 96000000) { ++ ret = regmap_update_bits(cmn_pll->regmap, CMN_PLL_REFCLK_CONFIG, ++ CMN_PLL_REFCLK_DIV, ++ FIELD_PREP(CMN_PLL_REFCLK_DIV, 2)); ++ if (ret) ++ return ret; ++ ++ ret = regmap_update_bits(cmn_pll->regmap, CMN_PLL_REFCLK_SRC_SELECTION, ++ CMN_PLL_REFCLK_SRC_DIV, ++ FIELD_PREP(CMN_PLL_REFCLK_SRC_DIV, 0)); ++ if (ret) ++ return ret; ++ } ++ ++ /* Enable PLL locked detect. */ ++ ret = regmap_set_bits(cmn_pll->regmap, CMN_PLL_CTRL, ++ CMN_PLL_CTRL_LOCK_DETECT_EN); ++ if (ret) ++ return ret; ++ ++ /* ++ * Reset the CMN PLL block to ensure the updated configurations ++ * take effect. ++ */ ++ ret = regmap_clear_bits(cmn_pll->regmap, CMN_PLL_POWER_ON_AND_RESET, ++ CMN_ANA_EN_SW_RSTN); ++ if (ret) ++ return ret; ++ ++ usleep_range(1000, 1200); ++ ret = regmap_set_bits(cmn_pll->regmap, CMN_PLL_POWER_ON_AND_RESET, ++ CMN_ANA_EN_SW_RSTN); ++ if (ret) ++ return ret; ++ ++ /* Stability check of CMN PLL output clocks. */ ++ return regmap_read_poll_timeout(cmn_pll->regmap, CMN_PLL_LOCKED, val, ++ (val & CMN_PLL_CLKS_LOCKED), ++ 100, 100 * USEC_PER_MSEC); ++} ++ ++static const struct clk_ops clk_cmn_pll_ops = { ++ .recalc_rate = clk_cmn_pll_recalc_rate, ++ .determine_rate = clk_cmn_pll_determine_rate, ++ .set_rate = clk_cmn_pll_set_rate, ++}; ++ ++static struct clk_hw *ipq_cmn_pll_clk_hw_register(struct platform_device *pdev) ++{ ++ struct clk_parent_data pdata = { .index = 0 }; ++ struct device *dev = &pdev->dev; ++ struct clk_init_data init = {}; ++ struct clk_cmn_pll *cmn_pll; ++ struct regmap *regmap; ++ void __iomem *base; ++ int ret; ++ ++ base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(base)) ++ return ERR_CAST(base); ++ ++ regmap = devm_regmap_init_mmio(dev, base, &ipq_cmn_pll_regmap_config); ++ if (IS_ERR(regmap)) ++ return ERR_CAST(regmap); ++ ++ cmn_pll = devm_kzalloc(dev, sizeof(*cmn_pll), GFP_KERNEL); ++ if (!cmn_pll) ++ return ERR_PTR(-ENOMEM); ++ ++ init.name = "cmn_pll"; ++ init.parent_data = &pdata; ++ init.num_parents = 1; ++ init.ops = &clk_cmn_pll_ops; ++ ++ cmn_pll->hw.init = &init; ++ cmn_pll->regmap = regmap; ++ ++ ret = devm_clk_hw_register(dev, &cmn_pll->hw); ++ if (ret) ++ return ERR_PTR(ret); ++ ++ return &cmn_pll->hw; ++} ++ ++static int ipq_cmn_pll_register_clks(struct platform_device *pdev) ++{ ++ const struct cmn_pll_fixed_output_clk *fixed_clk; ++ struct clk_hw_onecell_data *hw_data; ++ struct device *dev = &pdev->dev; ++ struct clk_hw *cmn_pll_hw; ++ unsigned int num_clks; ++ struct clk_hw *hw; ++ int ret, i; ++ ++ fixed_clk = ipq9574_output_clks; ++ num_clks = ARRAY_SIZE(ipq9574_output_clks); ++ ++ hw_data = devm_kzalloc(dev, struct_size(hw_data, hws, num_clks + 1), ++ GFP_KERNEL); ++ if (!hw_data) ++ return -ENOMEM; ++ ++ /* ++ * Register the CMN PLL clock, which is the parent clock of ++ * the fixed rate output clocks. ++ */ ++ cmn_pll_hw = ipq_cmn_pll_clk_hw_register(pdev); ++ if (IS_ERR(cmn_pll_hw)) ++ return PTR_ERR(cmn_pll_hw); ++ ++ /* Register the fixed rate output clocks. */ ++ for (i = 0; i < num_clks; i++) { ++ hw = clk_hw_register_fixed_rate_parent_hw(dev, fixed_clk[i].name, ++ cmn_pll_hw, 0, ++ fixed_clk[i].rate); ++ if (IS_ERR(hw)) { ++ ret = PTR_ERR(hw); ++ goto unregister_fixed_clk; ++ } ++ ++ hw_data->hws[fixed_clk[i].id] = hw; ++ } ++ ++ /* ++ * Provide the CMN PLL clock. The clock rate of CMN PLL ++ * is configured to 12 GHZ by DT property assigned-clock-rates-u64. ++ */ ++ hw_data->hws[CMN_PLL_CLK] = cmn_pll_hw; ++ hw_data->num = num_clks + 1; ++ ++ ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, hw_data); ++ if (ret) ++ goto unregister_fixed_clk; ++ ++ platform_set_drvdata(pdev, hw_data); ++ ++ return 0; ++ ++unregister_fixed_clk: ++ while (i > 0) ++ clk_hw_unregister(hw_data->hws[fixed_clk[--i].id]); ++ ++ return ret; ++} ++ ++static int ipq_cmn_pll_clk_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ int ret; ++ ++ ret = devm_pm_runtime_enable(dev); ++ if (ret) ++ return ret; ++ ++ ret = devm_pm_clk_create(dev); ++ if (ret) ++ return ret; ++ ++ /* ++ * To access the CMN PLL registers, the GCC AHB & SYS clocks ++ * of CMN PLL block need to be enabled. ++ */ ++ ret = pm_clk_add(dev, "ahb"); ++ if (ret) ++ return dev_err_probe(dev, ret, "Fail to add AHB clock\n"); ++ ++ ret = pm_clk_add(dev, "sys"); ++ if (ret) ++ return dev_err_probe(dev, ret, "Fail to add SYS clock\n"); ++ ++ ret = pm_runtime_resume_and_get(dev); ++ if (ret) ++ return ret; ++ ++ /* Register CMN PLL clock and fixed rate output clocks. */ ++ ret = ipq_cmn_pll_register_clks(pdev); ++ pm_runtime_put(dev); ++ if (ret) ++ return dev_err_probe(dev, ret, ++ "Fail to register CMN PLL clocks\n"); ++ ++ return 0; ++} ++ ++static void ipq_cmn_pll_clk_remove(struct platform_device *pdev) ++{ ++ struct clk_hw_onecell_data *hw_data = platform_get_drvdata(pdev); ++ int i; ++ ++ /* ++ * The clock with index CMN_PLL_CLK is unregistered by ++ * device management. ++ */ ++ for (i = 0; i < hw_data->num; i++) { ++ if (i != CMN_PLL_CLK) ++ clk_hw_unregister(hw_data->hws[i]); ++ } ++} ++ ++static const struct dev_pm_ops ipq_cmn_pll_pm_ops = { ++ SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) ++}; ++ ++static const struct of_device_id ipq_cmn_pll_clk_ids[] = { ++ { .compatible = "qcom,ipq9574-cmn-pll", }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, ipq_cmn_pll_clk_ids); ++ ++static struct platform_driver ipq_cmn_pll_clk_driver = { ++ .probe = ipq_cmn_pll_clk_probe, ++ .remove = ipq_cmn_pll_clk_remove, ++ .driver = { ++ .name = "ipq_cmn_pll", ++ .of_match_table = ipq_cmn_pll_clk_ids, ++ .pm = &ipq_cmn_pll_pm_ops, ++ }, ++}; ++module_platform_driver(ipq_cmn_pll_clk_driver); ++ ++MODULE_DESCRIPTION("Qualcomm Technologies, Inc. IPQ CMN PLL Driver"); ++MODULE_LICENSE("GPL"); diff --git a/target/linux/qualcommbe/patches-6.12/0008-v6.14-arm64-dts-qcom-ipq9574-Add-CMN-PLL-node.patch b/target/linux/qualcommbe/patches-6.12/0008-v6.14-arm64-dts-qcom-ipq9574-Add-CMN-PLL-node.patch new file mode 100644 index 00000000000..deaa7ca891c --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0008-v6.14-arm64-dts-qcom-ipq9574-Add-CMN-PLL-node.patch @@ -0,0 +1,122 @@ +From 20a3597d994c8ac372bbb66d9f11bccb7f405154 Mon Sep 17 00:00:00 2001 +From: Luo Jie +Date: Fri, 3 Jan 2025 15:31:37 +0800 +Subject: [PATCH 08/22] v6.14: arm64: dts: qcom: ipq9574: Add CMN PLL node + +The CMN PLL clock controller allows selection of an input clock rate +from a defined set of input clock rates. It in-turn supplies fixed +rate output clocks to the hardware blocks that provide the ethernet +functions such as PPE (Packet Process Engine) and connected switch or +PHY, and to GCC. + +The reference clock of CMN PLL is routed from XO to the CMN PLL through +the internal WiFi block. +.XO (48 MHZ or 96 MHZ)-->WiFi (multiplier/divider)-->48 MHZ to CMN PLL. + +The reference input clock from WiFi to CMN PLL is fully controlled by +the bootstrap pins which select the XO frequency (48 MHZ or 96 MHZ). +Based on this frequency, the divider in the internal Wi-Fi block is +automatically configured by hardware (1 for 48 MHZ, 2 for 96 MHZ), to +ensure output clock to CMN PLL is 48 MHZ. + +Signed-off-by: Luo Jie +Reviewed-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20250103-qcom_ipq_cmnpll-v8-4-c89fb4d4849d@quicinc.com +Signed-off-by: Bjorn Andersson +--- + .../boot/dts/qcom/ipq9574-rdp-common.dtsi | 17 +++++++++++- + arch/arm64/boot/dts/qcom/ipq9574.dtsi | 26 ++++++++++++++++++- + 2 files changed, 41 insertions(+), 2 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi +@@ -3,7 +3,7 @@ + * IPQ9574 RDP board common device tree source + * + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. +- * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. ++ * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + + /dts-v1/; +@@ -164,6 +164,21 @@ + status = "okay"; + }; + ++/* ++ * The bootstrap pins for the board select the XO clock frequency ++ * (48 MHZ or 96 MHZ used for different RDP type board). This setting ++ * automatically enables the right dividers, to ensure the reference ++ * clock output from WiFi to the CMN PLL is 48 MHZ. ++ */ ++&ref_48mhz_clk { ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ + &xo_board_clk { + clock-frequency = <24000000>; + }; ++ ++&xo_clk { ++ clock-frequency = <48000000>; ++}; +--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi +@@ -3,10 +3,11 @@ + * IPQ9574 SoC device tree source + * + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. +- * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. ++ * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + + #include ++#include + #include + #include + #include +@@ -19,6 +20,12 @@ + #size-cells = <2>; + + clocks { ++ ref_48mhz_clk: ref-48mhz-clk { ++ compatible = "fixed-factor-clock"; ++ clocks = <&xo_clk>; ++ #clock-cells = <0>; ++ }; ++ + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; +@@ -28,6 +35,11 @@ + compatible = "fixed-clock"; + #clock-cells = <0>; + }; ++ ++ xo_clk: xo-clk { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ }; + }; + + cpus { +@@ -335,6 +347,18 @@ + status = "disabled"; + }; + ++ cmn_pll: clock-controller@9b000 { ++ compatible = "qcom,ipq9574-cmn-pll"; ++ reg = <0x0009b000 0x800>; ++ clocks = <&ref_48mhz_clk>, ++ <&gcc GCC_CMN_12GPLL_AHB_CLK>, ++ <&gcc GCC_CMN_12GPLL_SYS_CLK>; ++ clock-names = "ref", "ahb", "sys"; ++ #clock-cells = <1>; ++ assigned-clocks = <&cmn_pll CMN_PLL_CLK>; ++ assigned-clock-rates-u64 = /bits/ 64 <12000000000>; ++ }; ++ + qfprom: efuse@a4000 { + compatible = "qcom,ipq9574-qfprom", "qcom,qfprom"; + reg = <0x000a4000 0x5a1>; diff --git a/target/linux/qualcommbe/patches-6.12/0009-v6.14-arm64-dts-qcom-ipq9574-Update-xo_board_clk-to-.patch b/target/linux/qualcommbe/patches-6.12/0009-v6.14-arm64-dts-qcom-ipq9574-Update-xo_board_clk-to-.patch new file mode 100644 index 00000000000..e27d7791a73 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0009-v6.14-arm64-dts-qcom-ipq9574-Update-xo_board_clk-to-.patch @@ -0,0 +1,48 @@ +From 62307c5e153de617cb0827509fb964df051caaac Mon Sep 17 00:00:00 2001 +From: Luo Jie +Date: Fri, 3 Jan 2025 15:31:38 +0800 +Subject: [PATCH 09/22] v6.14: arm64: dts: qcom: ipq9574: Update xo_board_clk + to use fixed factor clock + +xo_board_clk is fixed to 24 MHZ, which is routed from WiFi output clock +48 MHZ (also being the reference clock of CMN PLL) divided 2 by analog +block routing channel. + +Reviewed-by: Konrad Dybcio +Signed-off-by: Luo Jie +Link: https://lore.kernel.org/r/20250103-qcom_ipq_cmnpll-v8-5-c89fb4d4849d@quicinc.com +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi | 7 ++++++- + arch/arm64/boot/dts/qcom/ipq9574.dtsi | 3 ++- + 2 files changed, 8 insertions(+), 2 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi +@@ -175,8 +175,13 @@ + clock-mult = <1>; + }; + ++/* ++ * The frequency of xo_board_clk is fixed to 24 MHZ, which is routed ++ * from WiFi output clock 48 MHZ divided by 2. ++ */ + &xo_board_clk { +- clock-frequency = <24000000>; ++ clock-div = <2>; ++ clock-mult = <1>; + }; + + &xo_clk { +--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi +@@ -32,7 +32,8 @@ + }; + + xo_board_clk: xo-board-clk { +- compatible = "fixed-clock"; ++ compatible = "fixed-factor-clock"; ++ clocks = <&ref_48mhz_clk>; + #clock-cells = <0>; + }; + diff --git a/target/linux/qualcommbe/patches-6.12/0010-v6.14-net-phy-add-phy_inband_caps.patch b/target/linux/qualcommbe/patches-6.12/0010-v6.14-net-phy-add-phy_inband_caps.patch new file mode 100644 index 00000000000..0cd3680176a --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0010-v6.14-net-phy-add-phy_inband_caps.patch @@ -0,0 +1,118 @@ +From 7b0f0f00a301906cc78d3c8974ea14ad8db29f0c Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Tue, 3 Dec 2024 15:31:02 +0000 +Subject: [PATCH 10/22] v6.14: net: phy: add phy_inband_caps() + +Add a method to query the PHY's in-band capabilities for a PHY +interface mode. + +Where the interface mode does not have in-band capability, or the PHY +driver has not been updated to return this information, then +phy_inband_caps() should return zero. Otherwise, PHY drivers will +return a value consisting of the following flags: + +LINK_INBAND_DISABLE indicates that the hardware does not support +in-band signalling, or can have in-band signalling configured via +software to be disabled. + +LINK_INBAND_ENABLE indicates that the hardware will use in-band +signalling, or can have in-band signalling configured via software +to be enabled. + +LINK_INBAND_BYPASS indicates that the hardware has the ability to +bypass in-band signalling when enabled after a timeout if the link +partner does not respond to its in-band signalling. + +This reports the PHY capabilities for the particular interface mode, +not the current configuration. + +Reviewed-by: Andrew Lunn +Signed-off-by: Russell King (Oracle) +Link: https://patch.msgid.link/E1tIUre-006ITz-KF@rmk-PC.armlinux.org.uk +Signed-off-by: Jakub Kicinski +--- + drivers/net/phy/phy.c | 21 +++++++++++++++++++++ + include/linux/phy.h | 28 ++++++++++++++++++++++++++++ + 2 files changed, 49 insertions(+) + +--- a/drivers/net/phy/phy.c ++++ b/drivers/net/phy/phy.c +@@ -1049,6 +1049,27 @@ static int phy_check_link_status(struct + } + + /** ++ * phy_inband_caps - query which in-band signalling modes are supported ++ * @phydev: a pointer to a &struct phy_device ++ * @interface: the interface mode for the PHY ++ * ++ * Returns zero if it is unknown what in-band signalling is supported by the ++ * PHY (e.g. because the PHY driver doesn't implement the method.) Otherwise, ++ * returns a bit mask of the LINK_INBAND_* values from ++ * &enum link_inband_signalling to describe which inband modes are supported ++ * by the PHY for this interface mode. ++ */ ++unsigned int phy_inband_caps(struct phy_device *phydev, ++ phy_interface_t interface) ++{ ++ if (phydev->drv && phydev->drv->inband_caps) ++ return phydev->drv->inband_caps(phydev, interface); ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(phy_inband_caps); ++ ++/** + * _phy_start_aneg - start auto-negotiation for this PHY device + * @phydev: the phy_device struct + * +--- a/include/linux/phy.h ++++ b/include/linux/phy.h +@@ -819,6 +819,24 @@ struct phy_tdr_config { + #define PHY_PAIR_ALL -1 + + /** ++ * enum link_inband_signalling - in-band signalling modes that are supported ++ * ++ * @LINK_INBAND_DISABLE: in-band signalling can be disabled ++ * @LINK_INBAND_ENABLE: in-band signalling can be enabled without bypass ++ * @LINK_INBAND_BYPASS: in-band signalling can be enabled with bypass ++ * ++ * The possible and required bits can only be used if the valid bit is set. ++ * If possible is clear, that means inband signalling can not be used. ++ * Required is only valid when possible is set, and means that inband ++ * signalling must be used. ++ */ ++enum link_inband_signalling { ++ LINK_INBAND_DISABLE = BIT(0), ++ LINK_INBAND_ENABLE = BIT(1), ++ LINK_INBAND_BYPASS = BIT(2), ++}; ++ ++/** + * struct phy_plca_cfg - Configuration of the PLCA (Physical Layer Collision + * Avoidance) Reconciliation Sublayer. + * +@@ -958,6 +976,14 @@ struct phy_driver { + int (*get_features)(struct phy_device *phydev); + + /** ++ * @inband_caps: query whether in-band is supported for the given PHY ++ * interface mode. Returns a bitmask of bits defined by enum ++ * link_inband_signalling. ++ */ ++ unsigned int (*inband_caps)(struct phy_device *phydev, ++ phy_interface_t interface); ++ ++ /** + * @get_rate_matching: Get the supported type of rate matching for a + * particular phy interface. This is used by phy consumers to determine + * whether to advertise lower-speed modes for that interface. It is +@@ -1842,6 +1868,8 @@ int phy_config_aneg(struct phy_device *p + int _phy_start_aneg(struct phy_device *phydev); + int phy_start_aneg(struct phy_device *phydev); + int phy_aneg_done(struct phy_device *phydev); ++unsigned int phy_inband_caps(struct phy_device *phydev, ++ phy_interface_t interface); + int phy_speed_down(struct phy_device *phydev, bool sync); + int phy_speed_up(struct phy_device *phydev); + bool phy_check_valid(int speed, int duplex, unsigned long *features); diff --git a/target/linux/qualcommbe/patches-6.12/0011-v6.14-net-phylink-add-pcs_inband_caps-method.patch b/target/linux/qualcommbe/patches-6.12/0011-v6.14-net-phylink-add-pcs_inband_caps-method.patch new file mode 100644 index 00000000000..689428cb9ee --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0011-v6.14-net-phylink-add-pcs_inband_caps-method.patch @@ -0,0 +1,159 @@ +From 2d530b1085104f6aa0dfa35c908ac7c531941bf6 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Tue, 3 Dec 2024 15:31:28 +0000 +Subject: [PATCH 11/22] v6.14: net: phylink: add pcs_inband_caps() method + +Add a pcs_inband_caps() method to query the PCS for its inband link +capabilities, and use this to determine whether link modes used with +optical SFPs can be supported. + +When a PCS does not provide a method, we allow inband negotiation to +be either on or off, making this a no-op until the pcs_inband_caps() +method is implemented by a PCS driver. + +Reviewed-by: Andrew Lunn +Signed-off-by: Russell King (Oracle) +Link: https://patch.msgid.link/E1tIUs4-006IUU-7K@rmk-PC.armlinux.org.uk +Signed-off-by: Jakub Kicinski +--- + drivers/net/phy/phylink.c | 60 +++++++++++++++++++++++++++++++++++++++ + include/linux/phylink.h | 17 +++++++++++ + 2 files changed, 77 insertions(+) + +--- a/drivers/net/phy/phylink.c ++++ b/drivers/net/phy/phylink.c +@@ -988,6 +988,15 @@ static void phylink_resolve_an_pause(str + } + } + ++static unsigned int phylink_pcs_inband_caps(struct phylink_pcs *pcs, ++ phy_interface_t interface) ++{ ++ if (pcs && pcs->ops->pcs_inband_caps) ++ return pcs->ops->pcs_inband_caps(pcs, interface); ++ ++ return 0; ++} ++ + static void phylink_pcs_pre_config(struct phylink_pcs *pcs, + phy_interface_t interface) + { +@@ -1041,6 +1050,24 @@ static void phylink_pcs_link_up(struct p + pcs->ops->pcs_link_up(pcs, neg_mode, interface, speed, duplex); + } + ++/* Query inband for a specific interface mode, asking the MAC for the ++ * PCS which will be used to handle the interface mode. ++ */ ++static unsigned int phylink_inband_caps(struct phylink *pl, ++ phy_interface_t interface) ++{ ++ struct phylink_pcs *pcs; ++ ++ if (!pl->mac_ops->mac_select_pcs) ++ return 0; ++ ++ pcs = pl->mac_ops->mac_select_pcs(pl->config, interface); ++ if (!pcs) ++ return 0; ++ ++ return phylink_pcs_inband_caps(pcs, interface); ++} ++ + static void phylink_pcs_poll_stop(struct phylink *pl) + { + if (pl->cfg_link_an_mode == MLO_AN_INBAND) +@@ -2532,6 +2559,26 @@ int phylink_ethtool_ksettings_get(struct + } + EXPORT_SYMBOL_GPL(phylink_ethtool_ksettings_get); + ++static bool phylink_validate_pcs_inband_autoneg(struct phylink *pl, ++ phy_interface_t interface, ++ unsigned long *adv) ++{ ++ unsigned int inband = phylink_inband_caps(pl, interface); ++ unsigned int mask; ++ ++ /* If the PCS doesn't implement inband support, be permissive. */ ++ if (!inband) ++ return true; ++ ++ if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, adv)) ++ mask = LINK_INBAND_ENABLE; ++ else ++ mask = LINK_INBAND_DISABLE; ++ ++ /* Check whether the PCS implements the required mode */ ++ return !!(inband & mask); ++} ++ + /** + * phylink_ethtool_ksettings_set() - set the link settings + * @pl: a pointer to a &struct phylink returned from phylink_create() +@@ -2667,6 +2714,13 @@ int phylink_ethtool_ksettings_set(struct + phylink_is_empty_linkmode(config.advertising)) + return -EINVAL; + ++ /* Validate the autonegotiation state. We don't have a PHY in this ++ * situation, so the PCS is the media-facing entity. ++ */ ++ if (!phylink_validate_pcs_inband_autoneg(pl, config.interface, ++ config.advertising)) ++ return -EINVAL; ++ + mutex_lock(&pl->state_mutex); + pl->link_config.speed = config.speed; + pl->link_config.duplex = config.duplex; +@@ -3351,6 +3405,12 @@ static int phylink_sfp_config_optical(st + phylink_dbg(pl, "optical SFP: chosen %s interface\n", + phy_modes(interface)); + ++ if (!phylink_validate_pcs_inband_autoneg(pl, interface, ++ config.advertising)) { ++ phylink_err(pl, "autoneg setting not compatible with PCS"); ++ return -EINVAL; ++ } ++ + config.interface = interface; + + /* Ignore errors if we're expecting a PHY to attach later */ +--- a/include/linux/phylink.h ++++ b/include/linux/phylink.h +@@ -419,6 +419,7 @@ struct phylink_pcs { + /** + * struct phylink_pcs_ops - MAC PCS operations structure. + * @pcs_validate: validate the link configuration. ++ * @pcs_inband_caps: query inband support for interface mode. + * @pcs_enable: enable the PCS. + * @pcs_disable: disable the PCS. + * @pcs_pre_config: pre-mac_config method (for errata) +@@ -434,6 +435,8 @@ struct phylink_pcs { + struct phylink_pcs_ops { + int (*pcs_validate)(struct phylink_pcs *pcs, unsigned long *supported, + const struct phylink_link_state *state); ++ unsigned int (*pcs_inband_caps)(struct phylink_pcs *pcs, ++ phy_interface_t interface); + int (*pcs_enable)(struct phylink_pcs *pcs); + void (*pcs_disable)(struct phylink_pcs *pcs); + void (*pcs_pre_config)(struct phylink_pcs *pcs, +@@ -471,6 +474,20 @@ int pcs_validate(struct phylink_pcs *pcs + const struct phylink_link_state *state); + + /** ++ * pcs_inband_caps - query PCS in-band capabilities for interface mode. ++ * @pcs: a pointer to a &struct phylink_pcs. ++ * @interface: interface mode to be queried ++ * ++ * Returns zero if it is unknown what in-band signalling is supported by the ++ * PHY (e.g. because the PHY driver doesn't implement the method.) Otherwise, ++ * returns a bit mask of the LINK_INBAND_* values from ++ * &enum link_inband_signalling to describe which inband modes are supported ++ * for this interface mode. ++ */ ++unsigned int pcs_inband_caps(struct phylink_pcs *pcs, ++ phy_interface_t interface); ++ ++/** + * pcs_enable() - enable the PCS. + * @pcs: a pointer to a &struct phylink_pcs. + */ diff --git a/target/linux/qualcommbe/patches-6.12/0016-v6.15-spi-dt-bindings-Introduce-qcom-spi-qpic-snand.patch b/target/linux/qualcommbe/patches-6.12/0016-v6.15-spi-dt-bindings-Introduce-qcom-spi-qpic-snand.patch new file mode 100644 index 00000000000..6a1627a67e8 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0016-v6.15-spi-dt-bindings-Introduce-qcom-spi-qpic-snand.patch @@ -0,0 +1,105 @@ +From 66fde1c5d29006127cc4fc5a12a0c42415c098bd Mon Sep 17 00:00:00 2001 +From: Md Sadre Alam +Date: Mon, 24 Feb 2025 16:44:13 +0530 +Subject: [PATCH 16/22] v6.15: spi: dt-bindings: Introduce qcom,spi-qpic-snand + +Document the QPIC-SPI-NAND flash controller present in the IPQ SoCs. +It can work both in serial and parallel mode and supports typical +SPI-NAND page cache operations. + +Reviewed-by: Krzysztof Kozlowski +Reviewed-by: Rob Herring (Arm) +Signed-off-by: Md Sadre Alam +Link: https://patch.msgid.link/20250224111414.2809669-2-quic_mdalam@quicinc.com +Signed-off-by: Mark Brown +--- + .../bindings/spi/qcom,spi-qpic-snand.yaml | 83 +++++++++++++++++++ + 1 file changed, 83 insertions(+) + create mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml + +--- /dev/null ++++ b/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml +@@ -0,0 +1,83 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/spi/qcom,spi-qpic-snand.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Qualcomm QPIC NAND controller ++ ++maintainers: ++ - Md sadre Alam ++ ++description: ++ The QCOM QPIC-SPI-NAND flash controller is an extended version of ++ the QCOM QPIC NAND flash controller. It can work both in serial ++ and parallel mode. It supports typical SPI-NAND page cache ++ operations in single, dual or quad IO mode with pipelined ECC ++ encoding/decoding using the QPIC ECC HW engine. ++ ++allOf: ++ - $ref: /schemas/spi/spi-controller.yaml# ++ ++properties: ++ compatible: ++ enum: ++ - qcom,ipq9574-snand ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ maxItems: 3 ++ ++ clock-names: ++ items: ++ - const: core ++ - const: aon ++ - const: iom ++ ++ dmas: ++ items: ++ - description: tx DMA channel ++ - description: rx DMA channel ++ - description: cmd DMA channel ++ ++ dma-names: ++ items: ++ - const: tx ++ - const: rx ++ - const: cmd ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - clock-names ++ ++unevaluatedProperties: false ++ ++examples: ++ - | ++ #include ++ spi@79b0000 { ++ compatible = "qcom,ipq9574-snand"; ++ reg = <0x1ac00000 0x800>; ++ ++ clocks = <&gcc GCC_QPIC_CLK>, ++ <&gcc GCC_QPIC_AHB_CLK>, ++ <&gcc GCC_QPIC_IO_MACRO_CLK>; ++ clock-names = "core", "aon", "iom"; ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ flash@0 { ++ compatible = "spi-nand"; ++ reg = <0>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ nand-ecc-engine = <&qpic_nand>; ++ nand-ecc-strength = <4>; ++ nand-ecc-step-size = <512>; ++ }; ++ }; diff --git a/target/linux/qualcommbe/patches-6.12/0018-v6.15-dt-bindings-clock-gcc-ipq9574-Add-definition-f.patch b/target/linux/qualcommbe/patches-6.12/0018-v6.15-dt-bindings-clock-gcc-ipq9574-Add-definition-f.patch new file mode 100644 index 00000000000..dfe655df940 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0018-v6.15-dt-bindings-clock-gcc-ipq9574-Add-definition-f.patch @@ -0,0 +1,25 @@ +From 25ce13ad8852f14835e650132ccf4fc0bf127699 Mon Sep 17 00:00:00 2001 +From: Devi Priya +Date: Thu, 13 Mar 2025 16:33:54 +0530 +Subject: [PATCH 18/22] v6.15: dt-bindings: clock: gcc-ipq9574: Add definition + for GPLL0_OUT_AUX + +Add the definition for GPLL0_OUT_AUX clock. + +Acked-by: Krzysztof Kozlowski +Signed-off-by: Devi Priya +Signed-off-by: Manikanta Mylavarapu +Link: https://lore.kernel.org/r/20250313110359.242491-2-quic_mmanikan@quicinc.com +Signed-off-by: Bjorn Andersson +--- + include/dt-bindings/clock/qcom,ipq9574-gcc.h | 1 + + 1 file changed, 1 insertion(+) + +--- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h ++++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h +@@ -220,4 +220,5 @@ + #define GCC_PCIE1_PIPE_CLK 211 + #define GCC_PCIE2_PIPE_CLK 212 + #define GCC_PCIE3_PIPE_CLK 213 ++#define GPLL0_OUT_AUX 214 + #endif diff --git a/target/linux/qualcommbe/patches-6.12/0019-v6.15-dt-bindings-clock-Add-ipq9574-NSSCC-clock-and-.patch b/target/linux/qualcommbe/patches-6.12/0019-v6.15-dt-bindings-clock-Add-ipq9574-NSSCC-clock-and-.patch new file mode 100644 index 00000000000..0552b07b1ed --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0019-v6.15-dt-bindings-clock-Add-ipq9574-NSSCC-clock-and-.patch @@ -0,0 +1,415 @@ +From 5ed04d121a8d24cc3151aa57a21a6c944ad6d7f3 Mon Sep 17 00:00:00 2001 +From: Devi Priya +Date: Thu, 13 Mar 2025 16:33:56 +0530 +Subject: [PATCH 19/22] v6.15: dt-bindings: clock: Add ipq9574 NSSCC clock and + reset definitions + +Add NSSCC clock and reset definitions for ipq9574. + +Reviewed-by: Krzysztof Kozlowski +Signed-off-by: Devi Priya +Signed-off-by: Manikanta Mylavarapu +Link: https://lore.kernel.org/r/20250313110359.242491-4-quic_mmanikan@quicinc.com +Signed-off-by: Bjorn Andersson +--- + .../bindings/clock/qcom,ipq9574-nsscc.yaml | 98 +++++++++++ + .../dt-bindings/clock/qcom,ipq9574-nsscc.h | 152 ++++++++++++++++++ + .../dt-bindings/reset/qcom,ipq9574-nsscc.h | 134 +++++++++++++++ + 3 files changed, 384 insertions(+) + create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml + create mode 100644 include/dt-bindings/clock/qcom,ipq9574-nsscc.h + create mode 100644 include/dt-bindings/reset/qcom,ipq9574-nsscc.h + +--- /dev/null ++++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml +@@ -0,0 +1,98 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/clock/qcom,ipq9574-nsscc.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574 ++ ++maintainers: ++ - Bjorn Andersson ++ - Anusha Rao ++ ++description: | ++ Qualcomm networking sub system clock control module provides the clocks, ++ resets on IPQ9574 ++ ++ See also:: ++ include/dt-bindings/clock/qcom,ipq9574-nsscc.h ++ include/dt-bindings/reset/qcom,ipq9574-nsscc.h ++ ++properties: ++ compatible: ++ const: qcom,ipq9574-nsscc ++ ++ clocks: ++ items: ++ - description: Board XO source ++ - description: CMN_PLL NSS 1200MHz (Bias PLL cc) clock source ++ - description: CMN_PLL PPE 353MHz (Bias PLL ubi nc) clock source ++ - description: GCC GPLL0 OUT AUX clock source ++ - description: Uniphy0 NSS Rx clock source ++ - description: Uniphy0 NSS Tx clock source ++ - description: Uniphy1 NSS Rx clock source ++ - description: Uniphy1 NSS Tx clock source ++ - description: Uniphy2 NSS Rx clock source ++ - description: Uniphy2 NSS Tx clock source ++ - description: GCC NSSCC clock source ++ ++ '#interconnect-cells': ++ const: 1 ++ ++ clock-names: ++ items: ++ - const: xo ++ - const: nss_1200 ++ - const: ppe_353 ++ - const: gpll0_out ++ - const: uniphy0_rx ++ - const: uniphy0_tx ++ - const: uniphy1_rx ++ - const: uniphy1_tx ++ - const: uniphy2_rx ++ - const: uniphy2_tx ++ - const: bus ++ ++required: ++ - compatible ++ - clocks ++ - clock-names ++ ++allOf: ++ - $ref: qcom,gcc.yaml# ++ ++unevaluatedProperties: false ++ ++examples: ++ - | ++ #include ++ #include ++ clock-controller@39b00000 { ++ compatible = "qcom,ipq9574-nsscc"; ++ reg = <0x39b00000 0x80000>; ++ clocks = <&xo_board_clk>, ++ <&cmn_pll NSS_1200MHZ_CLK>, ++ <&cmn_pll PPE_353MHZ_CLK>, ++ <&gcc GPLL0_OUT_AUX>, ++ <&uniphy 0>, ++ <&uniphy 1>, ++ <&uniphy 2>, ++ <&uniphy 3>, ++ <&uniphy 4>, ++ <&uniphy 5>, ++ <&gcc GCC_NSSCC_CLK>; ++ clock-names = "xo", ++ "nss_1200", ++ "ppe_353", ++ "gpll0_out", ++ "uniphy0_rx", ++ "uniphy0_tx", ++ "uniphy1_rx", ++ "uniphy1_tx", ++ "uniphy2_rx", ++ "uniphy2_tx", ++ "bus"; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; ++... +--- /dev/null ++++ b/include/dt-bindings/clock/qcom,ipq9574-nsscc.h +@@ -0,0 +1,152 @@ ++/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ ++/* ++ * Copyright (c) 2023, 2025 The Linux Foundation. All rights reserved. ++ */ ++ ++#ifndef _DT_BINDINGS_CLOCK_IPQ_NSSCC_9574_H ++#define _DT_BINDINGS_CLOCK_IPQ_NSSCC_9574_H ++ ++#define NSS_CC_CE_APB_CLK 0 ++#define NSS_CC_CE_AXI_CLK 1 ++#define NSS_CC_CE_CLK_SRC 2 ++#define NSS_CC_CFG_CLK_SRC 3 ++#define NSS_CC_CLC_AXI_CLK 4 ++#define NSS_CC_CLC_CLK_SRC 5 ++#define NSS_CC_CRYPTO_CLK 6 ++#define NSS_CC_CRYPTO_CLK_SRC 7 ++#define NSS_CC_CRYPTO_PPE_CLK 8 ++#define NSS_CC_HAQ_AHB_CLK 9 ++#define NSS_CC_HAQ_AXI_CLK 10 ++#define NSS_CC_HAQ_CLK_SRC 11 ++#define NSS_CC_IMEM_AHB_CLK 12 ++#define NSS_CC_IMEM_CLK_SRC 13 ++#define NSS_CC_IMEM_QSB_CLK 14 ++#define NSS_CC_INT_CFG_CLK_SRC 15 ++#define NSS_CC_NSS_CSR_CLK 16 ++#define NSS_CC_NSSNOC_CE_APB_CLK 17 ++#define NSS_CC_NSSNOC_CE_AXI_CLK 18 ++#define NSS_CC_NSSNOC_CLC_AXI_CLK 19 ++#define NSS_CC_NSSNOC_CRYPTO_CLK 20 ++#define NSS_CC_NSSNOC_HAQ_AHB_CLK 21 ++#define NSS_CC_NSSNOC_HAQ_AXI_CLK 22 ++#define NSS_CC_NSSNOC_IMEM_AHB_CLK 23 ++#define NSS_CC_NSSNOC_IMEM_QSB_CLK 24 ++#define NSS_CC_NSSNOC_NSS_CSR_CLK 25 ++#define NSS_CC_NSSNOC_PPE_CFG_CLK 26 ++#define NSS_CC_NSSNOC_PPE_CLK 27 ++#define NSS_CC_NSSNOC_UBI32_AHB0_CLK 28 ++#define NSS_CC_NSSNOC_UBI32_AXI0_CLK 29 ++#define NSS_CC_NSSNOC_UBI32_INT0_AHB_CLK 30 ++#define NSS_CC_NSSNOC_UBI32_NC_AXI0_1_CLK 31 ++#define NSS_CC_NSSNOC_UBI32_NC_AXI0_CLK 32 ++#define NSS_CC_PORT1_MAC_CLK 33 ++#define NSS_CC_PORT1_RX_CLK 34 ++#define NSS_CC_PORT1_RX_CLK_SRC 35 ++#define NSS_CC_PORT1_RX_DIV_CLK_SRC 36 ++#define NSS_CC_PORT1_TX_CLK 37 ++#define NSS_CC_PORT1_TX_CLK_SRC 38 ++#define NSS_CC_PORT1_TX_DIV_CLK_SRC 39 ++#define NSS_CC_PORT2_MAC_CLK 40 ++#define NSS_CC_PORT2_RX_CLK 41 ++#define NSS_CC_PORT2_RX_CLK_SRC 42 ++#define NSS_CC_PORT2_RX_DIV_CLK_SRC 43 ++#define NSS_CC_PORT2_TX_CLK 44 ++#define NSS_CC_PORT2_TX_CLK_SRC 45 ++#define NSS_CC_PORT2_TX_DIV_CLK_SRC 46 ++#define NSS_CC_PORT3_MAC_CLK 47 ++#define NSS_CC_PORT3_RX_CLK 48 ++#define NSS_CC_PORT3_RX_CLK_SRC 49 ++#define NSS_CC_PORT3_RX_DIV_CLK_SRC 50 ++#define NSS_CC_PORT3_TX_CLK 51 ++#define NSS_CC_PORT3_TX_CLK_SRC 52 ++#define NSS_CC_PORT3_TX_DIV_CLK_SRC 53 ++#define NSS_CC_PORT4_MAC_CLK 54 ++#define NSS_CC_PORT4_RX_CLK 55 ++#define NSS_CC_PORT4_RX_CLK_SRC 56 ++#define NSS_CC_PORT4_RX_DIV_CLK_SRC 57 ++#define NSS_CC_PORT4_TX_CLK 58 ++#define NSS_CC_PORT4_TX_CLK_SRC 59 ++#define NSS_CC_PORT4_TX_DIV_CLK_SRC 60 ++#define NSS_CC_PORT5_MAC_CLK 61 ++#define NSS_CC_PORT5_RX_CLK 62 ++#define NSS_CC_PORT5_RX_CLK_SRC 63 ++#define NSS_CC_PORT5_RX_DIV_CLK_SRC 64 ++#define NSS_CC_PORT5_TX_CLK 65 ++#define NSS_CC_PORT5_TX_CLK_SRC 66 ++#define NSS_CC_PORT5_TX_DIV_CLK_SRC 67 ++#define NSS_CC_PORT6_MAC_CLK 68 ++#define NSS_CC_PORT6_RX_CLK 69 ++#define NSS_CC_PORT6_RX_CLK_SRC 70 ++#define NSS_CC_PORT6_RX_DIV_CLK_SRC 71 ++#define NSS_CC_PORT6_TX_CLK 72 ++#define NSS_CC_PORT6_TX_CLK_SRC 73 ++#define NSS_CC_PORT6_TX_DIV_CLK_SRC 74 ++#define NSS_CC_PPE_CLK_SRC 75 ++#define NSS_CC_PPE_EDMA_CFG_CLK 76 ++#define NSS_CC_PPE_EDMA_CLK 77 ++#define NSS_CC_PPE_SWITCH_BTQ_CLK 78 ++#define NSS_CC_PPE_SWITCH_CFG_CLK 79 ++#define NSS_CC_PPE_SWITCH_CLK 80 ++#define NSS_CC_PPE_SWITCH_IPE_CLK 81 ++#define NSS_CC_UBI0_CLK_SRC 82 ++#define NSS_CC_UBI0_DIV_CLK_SRC 83 ++#define NSS_CC_UBI1_CLK_SRC 84 ++#define NSS_CC_UBI1_DIV_CLK_SRC 85 ++#define NSS_CC_UBI2_CLK_SRC 86 ++#define NSS_CC_UBI2_DIV_CLK_SRC 87 ++#define NSS_CC_UBI32_AHB0_CLK 88 ++#define NSS_CC_UBI32_AHB1_CLK 89 ++#define NSS_CC_UBI32_AHB2_CLK 90 ++#define NSS_CC_UBI32_AHB3_CLK 91 ++#define NSS_CC_UBI32_AXI0_CLK 92 ++#define NSS_CC_UBI32_AXI1_CLK 93 ++#define NSS_CC_UBI32_AXI2_CLK 94 ++#define NSS_CC_UBI32_AXI3_CLK 95 ++#define NSS_CC_UBI32_CORE0_CLK 96 ++#define NSS_CC_UBI32_CORE1_CLK 97 ++#define NSS_CC_UBI32_CORE2_CLK 98 ++#define NSS_CC_UBI32_CORE3_CLK 99 ++#define NSS_CC_UBI32_INTR0_AHB_CLK 100 ++#define NSS_CC_UBI32_INTR1_AHB_CLK 101 ++#define NSS_CC_UBI32_INTR2_AHB_CLK 102 ++#define NSS_CC_UBI32_INTR3_AHB_CLK 103 ++#define NSS_CC_UBI32_NC_AXI0_CLK 104 ++#define NSS_CC_UBI32_NC_AXI1_CLK 105 ++#define NSS_CC_UBI32_NC_AXI2_CLK 106 ++#define NSS_CC_UBI32_NC_AXI3_CLK 107 ++#define NSS_CC_UBI32_UTCM0_CLK 108 ++#define NSS_CC_UBI32_UTCM1_CLK 109 ++#define NSS_CC_UBI32_UTCM2_CLK 110 ++#define NSS_CC_UBI32_UTCM3_CLK 111 ++#define NSS_CC_UBI3_CLK_SRC 112 ++#define NSS_CC_UBI3_DIV_CLK_SRC 113 ++#define NSS_CC_UBI_AXI_CLK_SRC 114 ++#define NSS_CC_UBI_NC_AXI_BFDCD_CLK_SRC 115 ++#define NSS_CC_UNIPHY_PORT1_RX_CLK 116 ++#define NSS_CC_UNIPHY_PORT1_TX_CLK 117 ++#define NSS_CC_UNIPHY_PORT2_RX_CLK 118 ++#define NSS_CC_UNIPHY_PORT2_TX_CLK 119 ++#define NSS_CC_UNIPHY_PORT3_RX_CLK 120 ++#define NSS_CC_UNIPHY_PORT3_TX_CLK 121 ++#define NSS_CC_UNIPHY_PORT4_RX_CLK 122 ++#define NSS_CC_UNIPHY_PORT4_TX_CLK 123 ++#define NSS_CC_UNIPHY_PORT5_RX_CLK 124 ++#define NSS_CC_UNIPHY_PORT5_TX_CLK 125 ++#define NSS_CC_UNIPHY_PORT6_RX_CLK 126 ++#define NSS_CC_UNIPHY_PORT6_TX_CLK 127 ++#define NSS_CC_XGMAC0_PTP_REF_CLK 128 ++#define NSS_CC_XGMAC0_PTP_REF_DIV_CLK_SRC 129 ++#define NSS_CC_XGMAC1_PTP_REF_CLK 130 ++#define NSS_CC_XGMAC1_PTP_REF_DIV_CLK_SRC 131 ++#define NSS_CC_XGMAC2_PTP_REF_CLK 132 ++#define NSS_CC_XGMAC2_PTP_REF_DIV_CLK_SRC 133 ++#define NSS_CC_XGMAC3_PTP_REF_CLK 134 ++#define NSS_CC_XGMAC3_PTP_REF_DIV_CLK_SRC 135 ++#define NSS_CC_XGMAC4_PTP_REF_CLK 136 ++#define NSS_CC_XGMAC4_PTP_REF_DIV_CLK_SRC 137 ++#define NSS_CC_XGMAC5_PTP_REF_CLK 138 ++#define NSS_CC_XGMAC5_PTP_REF_DIV_CLK_SRC 139 ++#define UBI32_PLL 140 ++#define UBI32_PLL_MAIN 141 ++ ++#endif +--- /dev/null ++++ b/include/dt-bindings/reset/qcom,ipq9574-nsscc.h +@@ -0,0 +1,134 @@ ++/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ ++/* ++ * Copyright (c) 2023, 2025 The Linux Foundation. All rights reserved. ++ */ ++ ++#ifndef _DT_BINDINGS_RESET_IPQ_NSSCC_9574_H ++#define _DT_BINDINGS_RESET_IPQ_NSSCC_9574_H ++ ++#define EDMA_HW_RESET 0 ++#define NSS_CC_CE_BCR 1 ++#define NSS_CC_CLC_BCR 2 ++#define NSS_CC_EIP197_BCR 3 ++#define NSS_CC_HAQ_BCR 4 ++#define NSS_CC_IMEM_BCR 5 ++#define NSS_CC_MAC_BCR 6 ++#define NSS_CC_PPE_BCR 7 ++#define NSS_CC_UBI_BCR 8 ++#define NSS_CC_UNIPHY_BCR 9 ++#define UBI3_CLKRST_CLAMP_ENABLE 10 ++#define UBI3_CORE_CLAMP_ENABLE 11 ++#define UBI2_CLKRST_CLAMP_ENABLE 12 ++#define UBI2_CORE_CLAMP_ENABLE 13 ++#define UBI1_CLKRST_CLAMP_ENABLE 14 ++#define UBI1_CORE_CLAMP_ENABLE 15 ++#define UBI0_CLKRST_CLAMP_ENABLE 16 ++#define UBI0_CORE_CLAMP_ENABLE 17 ++#define NSSNOC_NSS_CSR_ARES 18 ++#define NSS_CSR_ARES 19 ++#define PPE_BTQ_ARES 20 ++#define PPE_IPE_ARES 21 ++#define PPE_ARES 22 ++#define PPE_CFG_ARES 23 ++#define PPE_EDMA_ARES 24 ++#define PPE_EDMA_CFG_ARES 25 ++#define CRY_PPE_ARES 26 ++#define NSSNOC_PPE_ARES 27 ++#define NSSNOC_PPE_CFG_ARES 28 ++#define PORT1_MAC_ARES 29 ++#define PORT2_MAC_ARES 30 ++#define PORT3_MAC_ARES 31 ++#define PORT4_MAC_ARES 32 ++#define PORT5_MAC_ARES 33 ++#define PORT6_MAC_ARES 34 ++#define XGMAC0_PTP_REF_ARES 35 ++#define XGMAC1_PTP_REF_ARES 36 ++#define XGMAC2_PTP_REF_ARES 37 ++#define XGMAC3_PTP_REF_ARES 38 ++#define XGMAC4_PTP_REF_ARES 39 ++#define XGMAC5_PTP_REF_ARES 40 ++#define HAQ_AHB_ARES 41 ++#define HAQ_AXI_ARES 42 ++#define NSSNOC_HAQ_AHB_ARES 43 ++#define NSSNOC_HAQ_AXI_ARES 44 ++#define CE_APB_ARES 45 ++#define CE_AXI_ARES 46 ++#define NSSNOC_CE_APB_ARES 47 ++#define NSSNOC_CE_AXI_ARES 48 ++#define CRYPTO_ARES 49 ++#define NSSNOC_CRYPTO_ARES 50 ++#define NSSNOC_NC_AXI0_1_ARES 51 ++#define UBI0_CORE_ARES 52 ++#define UBI1_CORE_ARES 53 ++#define UBI2_CORE_ARES 54 ++#define UBI3_CORE_ARES 55 ++#define NC_AXI0_ARES 56 ++#define UTCM0_ARES 57 ++#define NC_AXI1_ARES 58 ++#define UTCM1_ARES 59 ++#define NC_AXI2_ARES 60 ++#define UTCM2_ARES 61 ++#define NC_AXI3_ARES 62 ++#define UTCM3_ARES 63 ++#define NSSNOC_NC_AXI0_ARES 64 ++#define AHB0_ARES 65 ++#define INTR0_AHB_ARES 66 ++#define AHB1_ARES 67 ++#define INTR1_AHB_ARES 68 ++#define AHB2_ARES 69 ++#define INTR2_AHB_ARES 70 ++#define AHB3_ARES 71 ++#define INTR3_AHB_ARES 72 ++#define NSSNOC_AHB0_ARES 73 ++#define NSSNOC_INT0_AHB_ARES 74 ++#define AXI0_ARES 75 ++#define AXI1_ARES 76 ++#define AXI2_ARES 77 ++#define AXI3_ARES 78 ++#define NSSNOC_AXI0_ARES 79 ++#define IMEM_QSB_ARES 80 ++#define NSSNOC_IMEM_QSB_ARES 81 ++#define IMEM_AHB_ARES 82 ++#define NSSNOC_IMEM_AHB_ARES 83 ++#define UNIPHY_PORT1_RX_ARES 84 ++#define UNIPHY_PORT1_TX_ARES 85 ++#define UNIPHY_PORT2_RX_ARES 86 ++#define UNIPHY_PORT2_TX_ARES 87 ++#define UNIPHY_PORT3_RX_ARES 88 ++#define UNIPHY_PORT3_TX_ARES 89 ++#define UNIPHY_PORT4_RX_ARES 90 ++#define UNIPHY_PORT4_TX_ARES 91 ++#define UNIPHY_PORT5_RX_ARES 92 ++#define UNIPHY_PORT5_TX_ARES 93 ++#define UNIPHY_PORT6_RX_ARES 94 ++#define UNIPHY_PORT6_TX_ARES 95 ++#define PORT1_RX_ARES 96 ++#define PORT1_TX_ARES 97 ++#define PORT2_RX_ARES 98 ++#define PORT2_TX_ARES 99 ++#define PORT3_RX_ARES 100 ++#define PORT3_TX_ARES 101 ++#define PORT4_RX_ARES 102 ++#define PORT4_TX_ARES 103 ++#define PORT5_RX_ARES 104 ++#define PORT5_TX_ARES 105 ++#define PORT6_RX_ARES 106 ++#define PORT6_TX_ARES 107 ++#define PPE_FULL_RESET 108 ++#define UNIPHY0_SOFT_RESET 109 ++#define UNIPHY1_SOFT_RESET 110 ++#define UNIPHY2_SOFT_RESET 111 ++#define UNIPHY_PORT1_ARES 112 ++#define UNIPHY_PORT2_ARES 113 ++#define UNIPHY_PORT3_ARES 114 ++#define UNIPHY_PORT4_ARES 115 ++#define UNIPHY_PORT5_ARES 116 ++#define UNIPHY_PORT6_ARES 117 ++#define NSSPORT1_RESET 118 ++#define NSSPORT2_RESET 119 ++#define NSSPORT3_RESET 120 ++#define NSSPORT4_RESET 121 ++#define NSSPORT5_RESET 122 ++#define NSSPORT6_RESET 123 ++ ++#endif diff --git a/target/linux/qualcommbe/patches-6.12/0020-v6.15-clk-qcom-gcc-ipq9574-Add-support-for-gpll0_out.patch b/target/linux/qualcommbe/patches-6.12/0020-v6.15-clk-qcom-gcc-ipq9574-Add-support-for-gpll0_out.patch new file mode 100644 index 00000000000..357fb18a71f --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0020-v6.15-clk-qcom-gcc-ipq9574-Add-support-for-gpll0_out.patch @@ -0,0 +1,49 @@ +From c4e7d95921b074980ffd389254bcbfc045dd2a49 Mon Sep 17 00:00:00 2001 +From: Devi Priya +Date: Thu, 13 Mar 2025 16:33:55 +0530 +Subject: [PATCH 20/22] v6.15: clk: qcom: gcc-ipq9574: Add support for + gpll0_out_aux clock + +Add support for gpll0_out_aux clock which acts as the parent for +certain networking subsystem (nss) clocks. + +Reviewed-by: Dmitry Baryshkov +Signed-off-by: Devi Priya +Signed-off-by: Manikanta Mylavarapu +Link: https://lore.kernel.org/r/20250313110359.242491-3-quic_mmanikan@quicinc.com +Signed-off-by: Bjorn Andersson +--- + drivers/clk/qcom/gcc-ipq9574.c | 15 +++++++++++++++ + 1 file changed, 15 insertions(+) + +--- a/drivers/clk/qcom/gcc-ipq9574.c ++++ b/drivers/clk/qcom/gcc-ipq9574.c +@@ -108,6 +108,20 @@ static struct clk_alpha_pll_postdiv gpll + }, + }; + ++static struct clk_alpha_pll_postdiv gpll0_out_aux = { ++ .offset = 0x20000, ++ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], ++ .width = 4, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "gpll0_out_aux", ++ .parent_hws = (const struct clk_hw *[]) { ++ &gpll0_main.clkr.hw ++ }, ++ .num_parents = 1, ++ .ops = &clk_alpha_pll_postdiv_ro_ops, ++ }, ++}; ++ + static struct clk_alpha_pll gpll4_main = { + .offset = 0x22000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], +@@ -4222,6 +4236,7 @@ static struct clk_regmap *gcc_ipq9574_cl + [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr, + [GCC_PCIE2_PIPE_CLK] = &gcc_pcie2_pipe_clk.clkr, + [GCC_PCIE3_PIPE_CLK] = &gcc_pcie3_pipe_clk.clkr, ++ [GPLL0_OUT_AUX] = &gpll0_out_aux.clkr, + }; + + static const struct qcom_reset_map gcc_ipq9574_resets[] = { diff --git a/target/linux/qualcommbe/patches-6.12/0021-v6.15-clk-qcom-Add-NSS-clock-Controller-driver-for-I.patch b/target/linux/qualcommbe/patches-6.12/0021-v6.15-clk-qcom-Add-NSS-clock-Controller-driver-for-I.patch new file mode 100644 index 00000000000..e6d95f8bf38 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0021-v6.15-clk-qcom-Add-NSS-clock-Controller-driver-for-I.patch @@ -0,0 +1,3160 @@ +From 8b42bea7cf2a21e854becf29760a947bef5cde0b Mon Sep 17 00:00:00 2001 +From: Devi Priya +Date: Thu, 13 Mar 2025 16:33:57 +0530 +Subject: [PATCH 21/22] v6.15: clk: qcom: Add NSS clock Controller driver for + IPQ9574 + +Add Networking Sub System Clock Controller (NSSCC) driver for ipq9574 based +devices. + +Reviewed-by: Konrad Dybcio +Signed-off-by: Devi Priya +Signed-off-by: Manikanta Mylavarapu +Link: https://lore.kernel.org/r/20250313110359.242491-5-quic_mmanikan@quicinc.com +Signed-off-by: Bjorn Andersson +--- + drivers/clk/qcom/Kconfig | 7 + + drivers/clk/qcom/Makefile | 1 + + drivers/clk/qcom/nsscc-ipq9574.c | 3110 ++++++++++++++++++++++++++++++ + 3 files changed, 3118 insertions(+) + create mode 100644 drivers/clk/qcom/nsscc-ipq9574.c + +--- a/drivers/clk/qcom/Kconfig ++++ b/drivers/clk/qcom/Kconfig +@@ -264,6 +264,13 @@ config IPQ_GCC_9574 + i2c, USB, SD/eMMC, etc. Select this for the root clock + of ipq9574. + ++config IPQ_NSSCC_9574 ++ tristate "IPQ9574 NSS Clock Controller" ++ depends on ARM64 || COMPILE_TEST ++ depends on IPQ_GCC_9574 ++ help ++ Support for NSS clock controller on ipq9574 devices. ++ + config IPQ_NSSCC_QCA8K + tristate "QCA8K(QCA8386 or QCA8084) NSS Clock Controller" + depends on MDIO_BUS +--- a/drivers/clk/qcom/Makefile ++++ b/drivers/clk/qcom/Makefile +@@ -37,6 +37,7 @@ obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq601 + obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o + obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o + obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o ++obj-$(CONFIG_IPQ_NSSCC_9574) += nsscc-ipq9574.o + obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o + obj-$(CONFIG_IPQ_NSSCC_QCA8K) += nsscc-qca8k.o + obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o +--- /dev/null ++++ b/drivers/clk/qcom/nsscc-ipq9574.c +@@ -0,0 +1,3110 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (c) 2021, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2023, 2025 Qualcomm Innovation Center, Inc. All rights reserved. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include "clk-alpha-pll.h" ++#include "clk-branch.h" ++#include "clk-pll.h" ++#include "clk-rcg.h" ++#include "clk-regmap.h" ++#include "clk-regmap-divider.h" ++#include "clk-regmap-mux.h" ++#include "common.h" ++#include "reset.h" ++ ++/* Need to match the order of clocks in DT binding */ ++enum { ++ DT_XO, ++ DT_BIAS_PLL_CC_CLK, ++ DT_BIAS_PLL_UBI_NC_CLK, ++ DT_GCC_GPLL0_OUT_AUX, ++ DT_UNIPHY0_NSS_RX_CLK, ++ DT_UNIPHY0_NSS_TX_CLK, ++ DT_UNIPHY1_NSS_RX_CLK, ++ DT_UNIPHY1_NSS_TX_CLK, ++ DT_UNIPHY2_NSS_RX_CLK, ++ DT_UNIPHY2_NSS_TX_CLK, ++}; ++ ++enum { ++ P_XO, ++ P_BIAS_PLL_CC_CLK, ++ P_BIAS_PLL_UBI_NC_CLK, ++ P_GCC_GPLL0_OUT_AUX, ++ P_UBI32_PLL_OUT_MAIN, ++ P_UNIPHY0_NSS_RX_CLK, ++ P_UNIPHY0_NSS_TX_CLK, ++ P_UNIPHY1_NSS_RX_CLK, ++ P_UNIPHY1_NSS_TX_CLK, ++ P_UNIPHY2_NSS_RX_CLK, ++ P_UNIPHY2_NSS_TX_CLK, ++}; ++ ++static const struct alpha_pll_config ubi32_pll_config = { ++ .l = 0x3e, ++ .alpha = 0x6666, ++ .config_ctl_val = 0x200d4aa8, ++ .config_ctl_hi_val = 0x3c, ++ .main_output_mask = BIT(0), ++ .aux_output_mask = BIT(1), ++ .pre_div_val = 0x0, ++ .pre_div_mask = BIT(12), ++ .post_div_val = 0x0, ++ .post_div_mask = GENMASK(9, 8), ++ .alpha_en_mask = BIT(24), ++ .test_ctl_val = 0x1c0000c0, ++ .test_ctl_hi_val = 0x4000, ++}; ++ ++static struct clk_alpha_pll ubi32_pll_main = { ++ .offset = 0x28000, ++ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA], ++ .flags = SUPPORTS_DYNAMIC_UPDATE, ++ .clkr = { ++ .hw.init = &(const struct clk_init_data) { ++ .name = "ubi32_pll_main", ++ .parent_data = &(const struct clk_parent_data) { ++ .index = DT_XO, ++ }, ++ .num_parents = 1, ++ .ops = &clk_alpha_pll_huayra_ops, ++ }, ++ }, ++}; ++ ++static struct clk_alpha_pll_postdiv ubi32_pll = { ++ .offset = 0x28000, ++ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA], ++ .width = 2, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "ubi32_pll", ++ .parent_hws = (const struct clk_hw *[]) { ++ &ubi32_pll_main.clkr.hw ++ }, ++ .num_parents = 1, ++ .ops = &clk_alpha_pll_postdiv_ro_ops, ++ .flags = CLK_SET_RATE_PARENT, ++ }, ++}; ++ ++static const struct parent_map nss_cc_parent_map_0[] = { ++ { P_XO, 0 }, ++ { P_BIAS_PLL_CC_CLK, 1 }, ++ { P_UNIPHY0_NSS_RX_CLK, 2 }, ++ { P_UNIPHY0_NSS_TX_CLK, 3 }, ++ { P_UNIPHY1_NSS_RX_CLK, 4 }, ++ { P_UNIPHY1_NSS_TX_CLK, 5 }, ++}; ++ ++static const struct clk_parent_data nss_cc_parent_data_0[] = { ++ { .index = DT_XO }, ++ { .index = DT_BIAS_PLL_CC_CLK }, ++ { .index = DT_UNIPHY0_NSS_RX_CLK }, ++ { .index = DT_UNIPHY0_NSS_TX_CLK }, ++ { .index = DT_UNIPHY1_NSS_RX_CLK }, ++ { .index = DT_UNIPHY1_NSS_TX_CLK }, ++}; ++ ++static const struct parent_map nss_cc_parent_map_1[] = { ++ { P_XO, 0 }, ++ { P_BIAS_PLL_UBI_NC_CLK, 1 }, ++ { P_GCC_GPLL0_OUT_AUX, 2 }, ++ { P_BIAS_PLL_CC_CLK, 6 }, ++}; ++ ++static const struct clk_parent_data nss_cc_parent_data_1[] = { ++ { .index = DT_XO }, ++ { .index = DT_BIAS_PLL_UBI_NC_CLK }, ++ { .index = DT_GCC_GPLL0_OUT_AUX }, ++ { .index = DT_BIAS_PLL_CC_CLK }, ++}; ++ ++static const struct parent_map nss_cc_parent_map_2[] = { ++ { P_XO, 0 }, ++ { P_UBI32_PLL_OUT_MAIN, 1 }, ++ { P_GCC_GPLL0_OUT_AUX, 2 }, ++}; ++ ++static const struct clk_parent_data nss_cc_parent_data_2[] = { ++ { .index = DT_XO }, ++ { .hw = &ubi32_pll.clkr.hw }, ++ { .index = DT_GCC_GPLL0_OUT_AUX }, ++}; ++ ++static const struct parent_map nss_cc_parent_map_3[] = { ++ { P_XO, 0 }, ++ { P_BIAS_PLL_CC_CLK, 1 }, ++ { P_GCC_GPLL0_OUT_AUX, 2 }, ++}; ++ ++static const struct clk_parent_data nss_cc_parent_data_3[] = { ++ { .index = DT_XO }, ++ { .index = DT_BIAS_PLL_CC_CLK }, ++ { .index = DT_GCC_GPLL0_OUT_AUX }, ++}; ++ ++static const struct parent_map nss_cc_parent_map_4[] = { ++ { P_XO, 0 }, ++ { P_BIAS_PLL_CC_CLK, 1 }, ++ { P_UNIPHY0_NSS_RX_CLK, 2 }, ++ { P_UNIPHY0_NSS_TX_CLK, 3 }, ++}; ++ ++static const struct clk_parent_data nss_cc_parent_data_4[] = { ++ { .index = DT_XO }, ++ { .index = DT_BIAS_PLL_CC_CLK }, ++ { .index = DT_UNIPHY0_NSS_RX_CLK }, ++ { .index = DT_UNIPHY0_NSS_TX_CLK }, ++}; ++ ++static const struct parent_map nss_cc_parent_map_5[] = { ++ { P_XO, 0 }, ++ { P_BIAS_PLL_CC_CLK, 1 }, ++ { P_UNIPHY2_NSS_RX_CLK, 2 }, ++ { P_UNIPHY2_NSS_TX_CLK, 3 }, ++}; ++ ++static const struct clk_parent_data nss_cc_parent_data_5[] = { ++ { .index = DT_XO }, ++ { .index = DT_BIAS_PLL_CC_CLK }, ++ { .index = DT_UNIPHY2_NSS_RX_CLK }, ++ { .index = DT_UNIPHY2_NSS_TX_CLK }, ++}; ++ ++static const struct parent_map nss_cc_parent_map_6[] = { ++ { P_XO, 0 }, ++ { P_GCC_GPLL0_OUT_AUX, 2 }, ++ { P_BIAS_PLL_CC_CLK, 6 }, ++}; ++ ++static const struct clk_parent_data nss_cc_parent_data_6[] = { ++ { .index = DT_XO }, ++ { .index = DT_GCC_GPLL0_OUT_AUX }, ++ { .index = DT_BIAS_PLL_CC_CLK }, ++}; ++ ++static const struct parent_map nss_cc_parent_map_7[] = { ++ { P_XO, 0 }, ++ { P_UBI32_PLL_OUT_MAIN, 1 }, ++ { P_GCC_GPLL0_OUT_AUX, 2 }, ++ { P_BIAS_PLL_CC_CLK, 6 }, ++}; ++ ++static const struct clk_parent_data nss_cc_parent_data_7[] = { ++ { .index = DT_XO }, ++ { .hw = &ubi32_pll.clkr.hw }, ++ { .index = DT_GCC_GPLL0_OUT_AUX }, ++ { .index = DT_BIAS_PLL_CC_CLK }, ++}; ++ ++static const struct freq_tbl ftbl_nss_cc_ce_clk_src[] = { ++ F(24000000, P_XO, 1, 0, 0), ++ F(353000000, P_BIAS_PLL_UBI_NC_CLK, 1, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 nss_cc_ce_clk_src = { ++ .cmd_rcgr = 0x28404, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_1, ++ .freq_tbl = ftbl_nss_cc_ce_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ce_clk_src", ++ .parent_data = nss_cc_parent_data_1, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_1), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_nss_cc_cfg_clk_src[] = { ++ F(100000000, P_GCC_GPLL0_OUT_AUX, 8, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 nss_cc_cfg_clk_src = { ++ .cmd_rcgr = 0x28104, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_3, ++ .freq_tbl = ftbl_nss_cc_cfg_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_cfg_clk_src", ++ .parent_data = nss_cc_parent_data_3, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_3), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_nss_cc_clc_clk_src[] = { ++ F(533333333, P_GCC_GPLL0_OUT_AUX, 1.5, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 nss_cc_clc_clk_src = { ++ .cmd_rcgr = 0x28604, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_6, ++ .freq_tbl = ftbl_nss_cc_clc_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_clc_clk_src", ++ .parent_data = nss_cc_parent_data_6, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_6), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_nss_cc_crypto_clk_src[] = { ++ F(24000000, P_XO, 1, 0, 0), ++ F(300000000, P_BIAS_PLL_CC_CLK, 4, 0, 0), ++ F(600000000, P_BIAS_PLL_CC_CLK, 2, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 nss_cc_crypto_clk_src = { ++ .cmd_rcgr = 0x16008, ++ .mnd_width = 16, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_3, ++ .freq_tbl = ftbl_nss_cc_crypto_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_crypto_clk_src", ++ .parent_data = nss_cc_parent_data_3, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_3), ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_rcg2 nss_cc_haq_clk_src = { ++ .cmd_rcgr = 0x28304, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_1, ++ .freq_tbl = ftbl_nss_cc_ce_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_haq_clk_src", ++ .parent_data = nss_cc_parent_data_1, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_1), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_rcg2 nss_cc_imem_clk_src = { ++ .cmd_rcgr = 0xe008, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_1, ++ .freq_tbl = ftbl_nss_cc_ce_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_imem_clk_src", ++ .parent_data = nss_cc_parent_data_1, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_1), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_nss_cc_int_cfg_clk_src[] = { ++ F(200000000, P_GCC_GPLL0_OUT_AUX, 4, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 nss_cc_int_cfg_clk_src = { ++ .cmd_rcgr = 0x287b4, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_3, ++ .freq_tbl = ftbl_nss_cc_int_cfg_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_int_cfg_clk_src", ++ .parent_data = nss_cc_parent_data_3, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_3), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_25[] = { ++ C(P_UNIPHY0_NSS_RX_CLK, 12.5, 0, 0), ++ C(P_UNIPHY0_NSS_RX_CLK, 5, 0, 0), ++}; ++ ++static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_125[] = { ++ C(P_UNIPHY0_NSS_RX_CLK, 2.5, 0, 0), ++ C(P_UNIPHY0_NSS_RX_CLK, 1, 0, 0), ++}; ++ ++static const struct freq_multi_tbl ftbl_nss_cc_port1_rx_clk_src[] = { ++ FMS(24000000, P_XO, 1, 0, 0), ++ FM(25000000, ftbl_nss_cc_port1_rx_clk_src_25), ++ FMS(78125000, P_UNIPHY0_NSS_RX_CLK, 4, 0, 0), ++ FM(125000000, ftbl_nss_cc_port1_rx_clk_src_125), ++ FMS(312500000, P_UNIPHY0_NSS_RX_CLK, 1, 0, 0), ++ { } ++}; ++ ++static const struct freq_conf ftbl_nss_cc_port1_tx_clk_src_25[] = { ++ C(P_UNIPHY0_NSS_TX_CLK, 12.5, 0, 0), ++ C(P_UNIPHY0_NSS_TX_CLK, 5, 0, 0), ++}; ++ ++static const struct freq_conf ftbl_nss_cc_port1_tx_clk_src_125[] = { ++ C(P_UNIPHY0_NSS_TX_CLK, 2.5, 0, 0), ++ C(P_UNIPHY0_NSS_TX_CLK, 1, 0, 0), ++}; ++ ++static const struct freq_multi_tbl ftbl_nss_cc_port1_tx_clk_src[] = { ++ FMS(24000000, P_XO, 1, 0, 0), ++ FM(25000000, ftbl_nss_cc_port1_tx_clk_src_25), ++ FMS(78125000, P_UNIPHY0_NSS_TX_CLK, 4, 0, 0), ++ FM(125000000, ftbl_nss_cc_port1_tx_clk_src_125), ++ FMS(312500000, P_UNIPHY0_NSS_TX_CLK, 1, 0, 0), ++ { } ++}; ++ ++static const struct freq_conf ftbl_nss_cc_port5_rx_clk_src_25[] = { ++ C(P_UNIPHY1_NSS_RX_CLK, 12.5, 0, 0), ++ C(P_UNIPHY0_NSS_RX_CLK, 5, 0, 0), ++}; ++ ++static const struct freq_conf ftbl_nss_cc_port5_rx_clk_src_125[] = { ++ C(P_UNIPHY1_NSS_RX_CLK, 2.5, 0, 0), ++ C(P_UNIPHY0_NSS_RX_CLK, 1, 0, 0), ++}; ++ ++static const struct freq_conf ftbl_nss_cc_port5_rx_clk_src_312p5[] = { ++ C(P_UNIPHY1_NSS_RX_CLK, 1, 0, 0), ++ C(P_UNIPHY0_NSS_RX_CLK, 1, 0, 0), ++}; ++ ++static const struct freq_multi_tbl ftbl_nss_cc_port5_rx_clk_src[] = { ++ FMS(24000000, P_XO, 1, 0, 0), ++ FM(25000000, ftbl_nss_cc_port5_rx_clk_src_25), ++ FMS(78125000, P_UNIPHY1_NSS_RX_CLK, 4, 0, 0), ++ FM(125000000, ftbl_nss_cc_port5_rx_clk_src_125), ++ FMS(156250000, P_UNIPHY1_NSS_RX_CLK, 2, 0, 0), ++ FM(312500000, ftbl_nss_cc_port5_rx_clk_src_312p5), ++ { } ++}; ++ ++static const struct freq_conf ftbl_nss_cc_port5_tx_clk_src_25[] = { ++ C(P_UNIPHY1_NSS_TX_CLK, 12.5, 0, 0), ++ C(P_UNIPHY0_NSS_TX_CLK, 5, 0, 0), ++}; ++ ++static const struct freq_conf ftbl_nss_cc_port5_tx_clk_src_125[] = { ++ C(P_UNIPHY1_NSS_TX_CLK, 2.5, 0, 0), ++ C(P_UNIPHY0_NSS_TX_CLK, 1, 0, 0), ++}; ++ ++static const struct freq_conf ftbl_nss_cc_port5_tx_clk_src_312p5[] = { ++ C(P_UNIPHY1_NSS_TX_CLK, 1, 0, 0), ++ C(P_UNIPHY0_NSS_TX_CLK, 1, 0, 0), ++}; ++ ++static const struct freq_multi_tbl ftbl_nss_cc_port5_tx_clk_src[] = { ++ FMS(24000000, P_XO, 1, 0, 0), ++ FM(25000000, ftbl_nss_cc_port5_tx_clk_src_25), ++ FMS(78125000, P_UNIPHY1_NSS_TX_CLK, 4, 0, 0), ++ FM(125000000, ftbl_nss_cc_port5_tx_clk_src_125), ++ FMS(156250000, P_UNIPHY1_NSS_TX_CLK, 2, 0, 0), ++ FM(312500000, ftbl_nss_cc_port5_tx_clk_src_312p5), ++ { } ++}; ++ ++static const struct freq_conf ftbl_nss_cc_port6_rx_clk_src_25[] = { ++ C(P_UNIPHY2_NSS_RX_CLK, 12.5, 0, 0), ++ C(P_UNIPHY2_NSS_RX_CLK, 5, 0, 0), ++}; ++ ++static const struct freq_conf ftbl_nss_cc_port6_rx_clk_src_125[] = { ++ C(P_UNIPHY2_NSS_RX_CLK, 2.5, 0, 0), ++ C(P_UNIPHY2_NSS_RX_CLK, 1, 0, 0), ++}; ++ ++static const struct freq_multi_tbl ftbl_nss_cc_port6_rx_clk_src[] = { ++ FMS(24000000, P_XO, 1, 0, 0), ++ FM(25000000, ftbl_nss_cc_port6_rx_clk_src_25), ++ FMS(78125000, P_UNIPHY2_NSS_RX_CLK, 4, 0, 0), ++ FM(125000000, ftbl_nss_cc_port6_rx_clk_src_125), ++ FMS(156250000, P_UNIPHY2_NSS_RX_CLK, 2, 0, 0), ++ FMS(312500000, P_UNIPHY2_NSS_RX_CLK, 1, 0, 0), ++ { } ++}; ++ ++static const struct freq_conf ftbl_nss_cc_port6_tx_clk_src_25[] = { ++ C(P_UNIPHY2_NSS_TX_CLK, 12.5, 0, 0), ++ C(P_UNIPHY2_NSS_TX_CLK, 5, 0, 0), ++}; ++ ++static const struct freq_conf ftbl_nss_cc_port6_tx_clk_src_125[] = { ++ C(P_UNIPHY2_NSS_TX_CLK, 2.5, 0, 0), ++ C(P_UNIPHY2_NSS_TX_CLK, 1, 0, 0), ++}; ++ ++static const struct freq_multi_tbl ftbl_nss_cc_port6_tx_clk_src[] = { ++ FMS(24000000, P_XO, 1, 0, 0), ++ FM(25000000, ftbl_nss_cc_port6_tx_clk_src_25), ++ FMS(78125000, P_UNIPHY2_NSS_TX_CLK, 4, 0, 0), ++ FM(125000000, ftbl_nss_cc_port6_tx_clk_src_125), ++ FMS(156250000, P_UNIPHY2_NSS_TX_CLK, 2, 0, 0), ++ FMS(312500000, P_UNIPHY2_NSS_TX_CLK, 1, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 nss_cc_port1_rx_clk_src = { ++ .cmd_rcgr = 0x28110, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_4, ++ .freq_multi_tbl = ftbl_nss_cc_port1_rx_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port1_rx_clk_src", ++ .parent_data = nss_cc_parent_data_4, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_4), ++ .ops = &clk_rcg2_fm_ops, ++ }, ++}; ++ ++static struct clk_rcg2 nss_cc_port1_tx_clk_src = { ++ .cmd_rcgr = 0x2811c, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_4, ++ .freq_multi_tbl = ftbl_nss_cc_port1_tx_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port1_tx_clk_src", ++ .parent_data = nss_cc_parent_data_4, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_4), ++ .ops = &clk_rcg2_fm_ops, ++ }, ++}; ++ ++static struct clk_rcg2 nss_cc_port2_rx_clk_src = { ++ .cmd_rcgr = 0x28128, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_4, ++ .freq_multi_tbl = ftbl_nss_cc_port1_rx_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port2_rx_clk_src", ++ .parent_data = nss_cc_parent_data_4, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_4), ++ .ops = &clk_rcg2_fm_ops, ++ }, ++}; ++ ++static struct clk_rcg2 nss_cc_port2_tx_clk_src = { ++ .cmd_rcgr = 0x28134, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_4, ++ .freq_multi_tbl = ftbl_nss_cc_port1_tx_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port2_tx_clk_src", ++ .parent_data = nss_cc_parent_data_4, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_4), ++ .ops = &clk_rcg2_fm_ops, ++ }, ++}; ++ ++static struct clk_rcg2 nss_cc_port3_rx_clk_src = { ++ .cmd_rcgr = 0x28140, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_4, ++ .freq_multi_tbl = ftbl_nss_cc_port1_rx_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port3_rx_clk_src", ++ .parent_data = nss_cc_parent_data_4, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_4), ++ .ops = &clk_rcg2_fm_ops, ++ }, ++}; ++ ++static struct clk_rcg2 nss_cc_port3_tx_clk_src = { ++ .cmd_rcgr = 0x2814c, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_4, ++ .freq_multi_tbl = ftbl_nss_cc_port1_tx_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port3_tx_clk_src", ++ .parent_data = nss_cc_parent_data_4, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_4), ++ .ops = &clk_rcg2_fm_ops, ++ }, ++}; ++ ++static struct clk_rcg2 nss_cc_port4_rx_clk_src = { ++ .cmd_rcgr = 0x28158, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_4, ++ .freq_multi_tbl = ftbl_nss_cc_port1_rx_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port4_rx_clk_src", ++ .parent_data = nss_cc_parent_data_4, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_4), ++ .ops = &clk_rcg2_fm_ops, ++ }, ++}; ++ ++static struct clk_rcg2 nss_cc_port4_tx_clk_src = { ++ .cmd_rcgr = 0x28164, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_4, ++ .freq_multi_tbl = ftbl_nss_cc_port1_tx_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port4_tx_clk_src", ++ .parent_data = nss_cc_parent_data_4, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_4), ++ .ops = &clk_rcg2_fm_ops, ++ }, ++}; ++ ++static struct clk_rcg2 nss_cc_port5_rx_clk_src = { ++ .cmd_rcgr = 0x28170, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_0, ++ .freq_multi_tbl = ftbl_nss_cc_port5_rx_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port5_rx_clk_src", ++ .parent_data = nss_cc_parent_data_0, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_0), ++ .ops = &clk_rcg2_fm_ops, ++ }, ++}; ++ ++static struct clk_rcg2 nss_cc_port5_tx_clk_src = { ++ .cmd_rcgr = 0x2817c, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_0, ++ .freq_multi_tbl = ftbl_nss_cc_port5_tx_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port5_tx_clk_src", ++ .parent_data = nss_cc_parent_data_0, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_0), ++ .ops = &clk_rcg2_fm_ops, ++ }, ++}; ++ ++static struct clk_rcg2 nss_cc_port6_rx_clk_src = { ++ .cmd_rcgr = 0x28188, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_5, ++ .freq_multi_tbl = ftbl_nss_cc_port6_rx_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port6_rx_clk_src", ++ .parent_data = nss_cc_parent_data_5, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_5), ++ .ops = &clk_rcg2_fm_ops, ++ }, ++}; ++ ++static struct clk_rcg2 nss_cc_port6_tx_clk_src = { ++ .cmd_rcgr = 0x28194, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_5, ++ .freq_multi_tbl = ftbl_nss_cc_port6_tx_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port6_tx_clk_src", ++ .parent_data = nss_cc_parent_data_5, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_5), ++ .ops = &clk_rcg2_fm_ops, ++ }, ++}; ++ ++static struct clk_rcg2 nss_cc_ppe_clk_src = { ++ .cmd_rcgr = 0x28204, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_1, ++ .freq_tbl = ftbl_nss_cc_ce_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ppe_clk_src", ++ .parent_data = nss_cc_parent_data_1, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_1), ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_nss_cc_ubi0_clk_src[] = { ++ F(24000000, P_XO, 1, 0, 0), ++ F(187200000, P_UBI32_PLL_OUT_MAIN, 8, 0, 0), ++ F(748800000, P_UBI32_PLL_OUT_MAIN, 2, 0, 0), ++ F(1497600000, P_UBI32_PLL_OUT_MAIN, 1, 0, 0), ++ F(1689600000, P_UBI32_PLL_OUT_MAIN, 1, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 nss_cc_ubi0_clk_src = { ++ .cmd_rcgr = 0x28704, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_2, ++ .freq_tbl = ftbl_nss_cc_ubi0_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi0_clk_src", ++ .parent_data = nss_cc_parent_data_2, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_2), ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_rcg2 nss_cc_ubi1_clk_src = { ++ .cmd_rcgr = 0x2870c, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_2, ++ .freq_tbl = ftbl_nss_cc_ubi0_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi1_clk_src", ++ .parent_data = nss_cc_parent_data_2, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_2), ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_rcg2 nss_cc_ubi2_clk_src = { ++ .cmd_rcgr = 0x28714, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_2, ++ .freq_tbl = ftbl_nss_cc_ubi0_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi2_clk_src", ++ .parent_data = nss_cc_parent_data_2, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_2), ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_rcg2 nss_cc_ubi3_clk_src = { ++ .cmd_rcgr = 0x2871c, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_2, ++ .freq_tbl = ftbl_nss_cc_ubi0_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi3_clk_src", ++ .parent_data = nss_cc_parent_data_2, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_2), ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_rcg2 nss_cc_ubi_axi_clk_src = { ++ .cmd_rcgr = 0x28724, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_7, ++ .freq_tbl = ftbl_nss_cc_clc_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi_axi_clk_src", ++ .parent_data = nss_cc_parent_data_7, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_7), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_rcg2 nss_cc_ubi_nc_axi_bfdcd_clk_src = { ++ .cmd_rcgr = 0x2872c, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .parent_map = nss_cc_parent_map_1, ++ .freq_tbl = ftbl_nss_cc_ce_clk_src, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi_nc_axi_bfdcd_clk_src", ++ .parent_data = nss_cc_parent_data_1, ++ .num_parents = ARRAY_SIZE(nss_cc_parent_data_1), ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_regmap_div nss_cc_port1_rx_div_clk_src = { ++ .reg = 0x28118, ++ .shift = 0, ++ .width = 9, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port1_rx_div_clk_src", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port1_rx_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_regmap_div_ops, ++ }, ++}; ++ ++static struct clk_regmap_div nss_cc_port1_tx_div_clk_src = { ++ .reg = 0x28124, ++ .shift = 0, ++ .width = 9, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port1_tx_div_clk_src", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port1_tx_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_regmap_div_ops, ++ }, ++}; ++ ++static struct clk_regmap_div nss_cc_port2_rx_div_clk_src = { ++ .reg = 0x28130, ++ .shift = 0, ++ .width = 9, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port2_rx_div_clk_src", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port2_rx_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_regmap_div_ops, ++ }, ++}; ++ ++static struct clk_regmap_div nss_cc_port2_tx_div_clk_src = { ++ .reg = 0x2813c, ++ .shift = 0, ++ .width = 9, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port2_tx_div_clk_src", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port2_tx_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_regmap_div_ops, ++ }, ++}; ++ ++static struct clk_regmap_div nss_cc_port3_rx_div_clk_src = { ++ .reg = 0x28148, ++ .shift = 0, ++ .width = 9, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port3_rx_div_clk_src", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port3_rx_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_regmap_div_ops, ++ }, ++}; ++ ++static struct clk_regmap_div nss_cc_port3_tx_div_clk_src = { ++ .reg = 0x28154, ++ .shift = 0, ++ .width = 9, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port3_tx_div_clk_src", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port3_tx_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_regmap_div_ops, ++ }, ++}; ++ ++static struct clk_regmap_div nss_cc_port4_rx_div_clk_src = { ++ .reg = 0x28160, ++ .shift = 0, ++ .width = 9, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port4_rx_div_clk_src", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port4_rx_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_regmap_div_ops, ++ }, ++}; ++ ++static struct clk_regmap_div nss_cc_port4_tx_div_clk_src = { ++ .reg = 0x2816c, ++ .shift = 0, ++ .width = 9, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port4_tx_div_clk_src", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port4_tx_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_regmap_div_ops, ++ }, ++}; ++ ++static struct clk_regmap_div nss_cc_port5_rx_div_clk_src = { ++ .reg = 0x28178, ++ .shift = 0, ++ .width = 9, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port5_rx_div_clk_src", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port5_rx_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_regmap_div_ops, ++ }, ++}; ++ ++static struct clk_regmap_div nss_cc_port5_tx_div_clk_src = { ++ .reg = 0x28184, ++ .shift = 0, ++ .width = 9, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port5_tx_div_clk_src", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port5_tx_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_regmap_div_ops, ++ }, ++}; ++ ++static struct clk_regmap_div nss_cc_port6_rx_div_clk_src = { ++ .reg = 0x28190, ++ .shift = 0, ++ .width = 9, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port6_rx_div_clk_src", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port6_rx_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_regmap_div_ops, ++ }, ++}; ++ ++static struct clk_regmap_div nss_cc_port6_tx_div_clk_src = { ++ .reg = 0x2819c, ++ .shift = 0, ++ .width = 9, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port6_tx_div_clk_src", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port6_tx_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_regmap_div_ops, ++ }, ++}; ++ ++static struct clk_regmap_div nss_cc_ubi0_div_clk_src = { ++ .reg = 0x287a4, ++ .shift = 0, ++ .width = 4, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi0_div_clk_src", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ubi0_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_regmap_div_ro_ops, ++ }, ++}; ++ ++static struct clk_regmap_div nss_cc_ubi1_div_clk_src = { ++ .reg = 0x287a8, ++ .shift = 0, ++ .width = 4, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi1_div_clk_src", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ubi1_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_regmap_div_ro_ops, ++ }, ++}; ++ ++static struct clk_regmap_div nss_cc_ubi2_div_clk_src = { ++ .reg = 0x287ac, ++ .shift = 0, ++ .width = 4, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi2_div_clk_src", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ubi2_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_regmap_div_ro_ops, ++ }, ++}; ++ ++static struct clk_regmap_div nss_cc_ubi3_div_clk_src = { ++ .reg = 0x287b0, ++ .shift = 0, ++ .width = 4, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi3_div_clk_src", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ubi3_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_regmap_div_ro_ops, ++ }, ++}; ++ ++static struct clk_regmap_div nss_cc_xgmac0_ptp_ref_div_clk_src = { ++ .reg = 0x28214, ++ .shift = 0, ++ .width = 4, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_xgmac0_ptp_ref_div_clk_src", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ppe_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_regmap_div_ro_ops, ++ }, ++}; ++ ++static struct clk_regmap_div nss_cc_xgmac1_ptp_ref_div_clk_src = { ++ .reg = 0x28218, ++ .shift = 0, ++ .width = 4, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_xgmac1_ptp_ref_div_clk_src", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ppe_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_regmap_div_ro_ops, ++ }, ++}; ++ ++static struct clk_regmap_div nss_cc_xgmac2_ptp_ref_div_clk_src = { ++ .reg = 0x2821c, ++ .shift = 0, ++ .width = 4, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_xgmac2_ptp_ref_div_clk_src", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ppe_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_regmap_div_ro_ops, ++ }, ++}; ++ ++static struct clk_regmap_div nss_cc_xgmac3_ptp_ref_div_clk_src = { ++ .reg = 0x28220, ++ .shift = 0, ++ .width = 4, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_xgmac3_ptp_ref_div_clk_src", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ppe_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_regmap_div_ro_ops, ++ }, ++}; ++ ++static struct clk_regmap_div nss_cc_xgmac4_ptp_ref_div_clk_src = { ++ .reg = 0x28224, ++ .shift = 0, ++ .width = 4, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_xgmac4_ptp_ref_div_clk_src", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ppe_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_regmap_div_ro_ops, ++ }, ++}; ++ ++static struct clk_regmap_div nss_cc_xgmac5_ptp_ref_div_clk_src = { ++ .reg = 0x28228, ++ .shift = 0, ++ .width = 4, ++ .clkr.hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_xgmac5_ptp_ref_div_clk_src", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ppe_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_regmap_div_ro_ops, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ce_apb_clk = { ++ .halt_reg = 0x2840c, ++ .clkr = { ++ .enable_reg = 0x2840c, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ce_apb_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ce_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ce_axi_clk = { ++ .halt_reg = 0x28410, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28410, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ce_axi_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ce_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_clc_axi_clk = { ++ .halt_reg = 0x2860c, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x2860c, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_clc_axi_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_clc_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_crypto_clk = { ++ .halt_reg = 0x1601c, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x1601c, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_crypto_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_crypto_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_crypto_ppe_clk = { ++ .halt_reg = 0x28240, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28240, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_crypto_ppe_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ppe_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_haq_ahb_clk = { ++ .halt_reg = 0x2830c, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x2830c, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_haq_ahb_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_haq_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_haq_axi_clk = { ++ .halt_reg = 0x28310, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28310, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_haq_axi_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_haq_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_imem_ahb_clk = { ++ .halt_reg = 0xe018, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0xe018, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_imem_ahb_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_cfg_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_imem_qsb_clk = { ++ .halt_reg = 0xe010, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0xe010, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_imem_qsb_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_imem_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_nss_csr_clk = { ++ .halt_reg = 0x281d0, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x281d0, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_nss_csr_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_cfg_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_nssnoc_ce_apb_clk = { ++ .halt_reg = 0x28414, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28414, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_nssnoc_ce_apb_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ce_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_nssnoc_ce_axi_clk = { ++ .halt_reg = 0x28418, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28418, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_nssnoc_ce_axi_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ce_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_nssnoc_clc_axi_clk = { ++ .halt_reg = 0x28610, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28610, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_nssnoc_clc_axi_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_clc_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_nssnoc_crypto_clk = { ++ .halt_reg = 0x16020, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x16020, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_nssnoc_crypto_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_crypto_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_nssnoc_haq_ahb_clk = { ++ .halt_reg = 0x28314, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28314, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_nssnoc_haq_ahb_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_haq_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_nssnoc_haq_axi_clk = { ++ .halt_reg = 0x28318, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28318, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_nssnoc_haq_axi_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_haq_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_nssnoc_imem_ahb_clk = { ++ .halt_reg = 0xe01c, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0xe01c, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_nssnoc_imem_ahb_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_cfg_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_nssnoc_imem_qsb_clk = { ++ .halt_reg = 0xe014, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0xe014, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_nssnoc_imem_qsb_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_imem_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_nssnoc_nss_csr_clk = { ++ .halt_reg = 0x281d4, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x281d4, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_nssnoc_nss_csr_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_cfg_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_nssnoc_ppe_cfg_clk = { ++ .halt_reg = 0x28248, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28248, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_nssnoc_ppe_cfg_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ppe_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_nssnoc_ppe_clk = { ++ .halt_reg = 0x28244, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28244, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_nssnoc_ppe_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ppe_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_nssnoc_ubi32_ahb0_clk = { ++ .halt_reg = 0x28788, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28788, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_nssnoc_ubi32_ahb0_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_cfg_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_nssnoc_ubi32_axi0_clk = { ++ .halt_reg = 0x287a0, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x287a0, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_nssnoc_ubi32_axi0_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ubi_axi_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_nssnoc_ubi32_int0_ahb_clk = { ++ .halt_reg = 0x2878c, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x2878c, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_nssnoc_ubi32_int0_ahb_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_int_cfg_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_nssnoc_ubi32_nc_axi0_1_clk = { ++ .halt_reg = 0x287bc, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x287bc, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_nssnoc_ubi32_nc_axi0_1_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_nssnoc_ubi32_nc_axi0_clk = { ++ .halt_reg = 0x28764, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28764, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_nssnoc_ubi32_nc_axi0_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_port1_mac_clk = { ++ .halt_reg = 0x2824c, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x2824c, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port1_mac_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ppe_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_port1_rx_clk = { ++ .halt_reg = 0x281a0, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x281a0, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port1_rx_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port1_rx_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_port1_tx_clk = { ++ .halt_reg = 0x281a4, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x281a4, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port1_tx_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port1_tx_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_port2_mac_clk = { ++ .halt_reg = 0x28250, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28250, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port2_mac_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ppe_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_port2_rx_clk = { ++ .halt_reg = 0x281a8, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x281a8, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port2_rx_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port2_rx_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_port2_tx_clk = { ++ .halt_reg = 0x281ac, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x281ac, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port2_tx_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port2_tx_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_port3_mac_clk = { ++ .halt_reg = 0x28254, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28254, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port3_mac_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ppe_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_port3_rx_clk = { ++ .halt_reg = 0x281b0, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x281b0, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port3_rx_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port3_rx_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_port3_tx_clk = { ++ .halt_reg = 0x281b4, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x281b4, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port3_tx_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port3_tx_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_port4_mac_clk = { ++ .halt_reg = 0x28258, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28258, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port4_mac_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ppe_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_port4_rx_clk = { ++ .halt_reg = 0x281b8, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x281b8, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port4_rx_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port4_rx_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_port4_tx_clk = { ++ .halt_reg = 0x281bc, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x281bc, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port4_tx_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port4_tx_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_port5_mac_clk = { ++ .halt_reg = 0x2825c, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x2825c, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port5_mac_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ppe_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_port5_rx_clk = { ++ .halt_reg = 0x281c0, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x281c0, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port5_rx_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port5_rx_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_port5_tx_clk = { ++ .halt_reg = 0x281c4, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x281c4, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port5_tx_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port5_tx_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_port6_mac_clk = { ++ .halt_reg = 0x28260, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28260, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port6_mac_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ppe_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_port6_rx_clk = { ++ .halt_reg = 0x281c8, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x281c8, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port6_rx_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port6_rx_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_port6_tx_clk = { ++ .halt_reg = 0x281cc, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x281cc, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_port6_tx_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port6_tx_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ppe_edma_cfg_clk = { ++ .halt_reg = 0x2823c, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x2823c, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ppe_edma_cfg_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ppe_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ppe_edma_clk = { ++ .halt_reg = 0x28238, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28238, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ppe_edma_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ppe_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ppe_switch_btq_clk = { ++ .halt_reg = 0x2827c, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x2827c, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ppe_switch_btq_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ppe_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ppe_switch_cfg_clk = { ++ .halt_reg = 0x28234, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28234, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ppe_switch_cfg_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ppe_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ppe_switch_clk = { ++ .halt_reg = 0x28230, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28230, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ppe_switch_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ppe_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ppe_switch_ipe_clk = { ++ .halt_reg = 0x2822c, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x2822c, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ppe_switch_ipe_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ppe_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ubi32_ahb0_clk = { ++ .halt_reg = 0x28768, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28768, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi32_ahb0_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_cfg_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ubi32_ahb1_clk = { ++ .halt_reg = 0x28770, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28770, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi32_ahb1_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_cfg_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ubi32_ahb2_clk = { ++ .halt_reg = 0x28778, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28778, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi32_ahb2_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_cfg_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ubi32_ahb3_clk = { ++ .halt_reg = 0x28780, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28780, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi32_ahb3_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_cfg_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ubi32_axi0_clk = { ++ .halt_reg = 0x28790, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28790, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi32_axi0_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ubi_axi_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ubi32_axi1_clk = { ++ .halt_reg = 0x28794, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28794, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi32_axi1_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ubi_axi_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ubi32_axi2_clk = { ++ .halt_reg = 0x28798, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28798, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi32_axi2_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ubi_axi_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ubi32_axi3_clk = { ++ .halt_reg = 0x2879c, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x2879c, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi32_axi3_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ubi_axi_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ubi32_core0_clk = { ++ .halt_reg = 0x28734, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28734, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi32_core0_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ubi0_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ubi32_core1_clk = { ++ .halt_reg = 0x28738, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28738, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi32_core1_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ubi1_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ubi32_core2_clk = { ++ .halt_reg = 0x2873c, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x2873c, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi32_core2_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ubi2_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ubi32_core3_clk = { ++ .halt_reg = 0x28740, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28740, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi32_core3_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ubi3_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ubi32_intr0_ahb_clk = { ++ .halt_reg = 0x2876c, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x2876c, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi32_intr0_ahb_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_int_cfg_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ubi32_intr1_ahb_clk = { ++ .halt_reg = 0x28774, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28774, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi32_intr1_ahb_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_int_cfg_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ubi32_intr2_ahb_clk = { ++ .halt_reg = 0x2877c, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x2877c, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi32_intr2_ahb_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_int_cfg_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ubi32_intr3_ahb_clk = { ++ .halt_reg = 0x28784, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28784, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi32_intr3_ahb_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_int_cfg_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ubi32_nc_axi0_clk = { ++ .halt_reg = 0x28744, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28744, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi32_nc_axi0_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ubi32_nc_axi1_clk = { ++ .halt_reg = 0x2874c, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x2874c, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi32_nc_axi1_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ubi32_nc_axi2_clk = { ++ .halt_reg = 0x28754, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28754, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi32_nc_axi2_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ubi32_nc_axi3_clk = { ++ .halt_reg = 0x2875c, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x2875c, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi32_nc_axi3_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ubi32_utcm0_clk = { ++ .halt_reg = 0x28748, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28748, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi32_utcm0_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ubi32_utcm1_clk = { ++ .halt_reg = 0x28750, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28750, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi32_utcm1_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ubi32_utcm2_clk = { ++ .halt_reg = 0x28758, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28758, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi32_utcm2_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_ubi32_utcm3_clk = { ++ .halt_reg = 0x28760, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28760, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_ubi32_utcm3_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_uniphy_port1_rx_clk = { ++ .halt_reg = 0x28904, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28904, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_uniphy_port1_rx_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port1_rx_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_uniphy_port1_tx_clk = { ++ .halt_reg = 0x28908, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28908, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_uniphy_port1_tx_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port1_tx_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_uniphy_port2_rx_clk = { ++ .halt_reg = 0x2890c, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x2890c, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_uniphy_port2_rx_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port2_rx_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_uniphy_port2_tx_clk = { ++ .halt_reg = 0x28910, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28910, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_uniphy_port2_tx_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port2_tx_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_uniphy_port3_rx_clk = { ++ .halt_reg = 0x28914, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28914, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_uniphy_port3_rx_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port3_rx_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_uniphy_port3_tx_clk = { ++ .halt_reg = 0x28918, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28918, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_uniphy_port3_tx_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port3_tx_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_uniphy_port4_rx_clk = { ++ .halt_reg = 0x2891c, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x2891c, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_uniphy_port4_rx_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port4_rx_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_uniphy_port4_tx_clk = { ++ .halt_reg = 0x28920, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28920, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_uniphy_port4_tx_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port4_tx_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_uniphy_port5_rx_clk = { ++ .halt_reg = 0x28924, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28924, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_uniphy_port5_rx_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port5_rx_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_uniphy_port5_tx_clk = { ++ .halt_reg = 0x28928, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28928, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_uniphy_port5_tx_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port5_tx_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_uniphy_port6_rx_clk = { ++ .halt_reg = 0x2892c, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x2892c, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_uniphy_port6_rx_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port6_rx_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_uniphy_port6_tx_clk = { ++ .halt_reg = 0x28930, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28930, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_uniphy_port6_tx_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_port6_tx_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_xgmac0_ptp_ref_clk = { ++ .halt_reg = 0x28264, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28264, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_xgmac0_ptp_ref_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_xgmac0_ptp_ref_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_xgmac1_ptp_ref_clk = { ++ .halt_reg = 0x28268, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28268, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_xgmac1_ptp_ref_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_xgmac1_ptp_ref_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_xgmac2_ptp_ref_clk = { ++ .halt_reg = 0x2826c, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x2826c, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_xgmac2_ptp_ref_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_xgmac2_ptp_ref_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_xgmac3_ptp_ref_clk = { ++ .halt_reg = 0x28270, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28270, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_xgmac3_ptp_ref_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_xgmac3_ptp_ref_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_xgmac4_ptp_ref_clk = { ++ .halt_reg = 0x28274, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28274, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_xgmac4_ptp_ref_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_xgmac4_ptp_ref_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_cc_xgmac5_ptp_ref_clk = { ++ .halt_reg = 0x28278, ++ .halt_check = BRANCH_HALT, ++ .clkr = { ++ .enable_reg = 0x28278, ++ .enable_mask = BIT(0), ++ .hw.init = &(const struct clk_init_data) { ++ .name = "nss_cc_xgmac5_ptp_ref_clk", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &nss_cc_xgmac5_ptp_ref_div_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_regmap *nss_cc_ipq9574_clocks[] = { ++ [NSS_CC_CE_APB_CLK] = &nss_cc_ce_apb_clk.clkr, ++ [NSS_CC_CE_AXI_CLK] = &nss_cc_ce_axi_clk.clkr, ++ [NSS_CC_CE_CLK_SRC] = &nss_cc_ce_clk_src.clkr, ++ [NSS_CC_CFG_CLK_SRC] = &nss_cc_cfg_clk_src.clkr, ++ [NSS_CC_CLC_AXI_CLK] = &nss_cc_clc_axi_clk.clkr, ++ [NSS_CC_CLC_CLK_SRC] = &nss_cc_clc_clk_src.clkr, ++ [NSS_CC_CRYPTO_CLK] = &nss_cc_crypto_clk.clkr, ++ [NSS_CC_CRYPTO_CLK_SRC] = &nss_cc_crypto_clk_src.clkr, ++ [NSS_CC_CRYPTO_PPE_CLK] = &nss_cc_crypto_ppe_clk.clkr, ++ [NSS_CC_HAQ_AHB_CLK] = &nss_cc_haq_ahb_clk.clkr, ++ [NSS_CC_HAQ_AXI_CLK] = &nss_cc_haq_axi_clk.clkr, ++ [NSS_CC_HAQ_CLK_SRC] = &nss_cc_haq_clk_src.clkr, ++ [NSS_CC_IMEM_AHB_CLK] = &nss_cc_imem_ahb_clk.clkr, ++ [NSS_CC_IMEM_CLK_SRC] = &nss_cc_imem_clk_src.clkr, ++ [NSS_CC_IMEM_QSB_CLK] = &nss_cc_imem_qsb_clk.clkr, ++ [NSS_CC_INT_CFG_CLK_SRC] = &nss_cc_int_cfg_clk_src.clkr, ++ [NSS_CC_NSS_CSR_CLK] = &nss_cc_nss_csr_clk.clkr, ++ [NSS_CC_NSSNOC_CE_APB_CLK] = &nss_cc_nssnoc_ce_apb_clk.clkr, ++ [NSS_CC_NSSNOC_CE_AXI_CLK] = &nss_cc_nssnoc_ce_axi_clk.clkr, ++ [NSS_CC_NSSNOC_CLC_AXI_CLK] = &nss_cc_nssnoc_clc_axi_clk.clkr, ++ [NSS_CC_NSSNOC_CRYPTO_CLK] = &nss_cc_nssnoc_crypto_clk.clkr, ++ [NSS_CC_NSSNOC_HAQ_AHB_CLK] = &nss_cc_nssnoc_haq_ahb_clk.clkr, ++ [NSS_CC_NSSNOC_HAQ_AXI_CLK] = &nss_cc_nssnoc_haq_axi_clk.clkr, ++ [NSS_CC_NSSNOC_IMEM_AHB_CLK] = &nss_cc_nssnoc_imem_ahb_clk.clkr, ++ [NSS_CC_NSSNOC_IMEM_QSB_CLK] = &nss_cc_nssnoc_imem_qsb_clk.clkr, ++ [NSS_CC_NSSNOC_NSS_CSR_CLK] = &nss_cc_nssnoc_nss_csr_clk.clkr, ++ [NSS_CC_NSSNOC_PPE_CFG_CLK] = &nss_cc_nssnoc_ppe_cfg_clk.clkr, ++ [NSS_CC_NSSNOC_PPE_CLK] = &nss_cc_nssnoc_ppe_clk.clkr, ++ [NSS_CC_NSSNOC_UBI32_AHB0_CLK] = &nss_cc_nssnoc_ubi32_ahb0_clk.clkr, ++ [NSS_CC_NSSNOC_UBI32_AXI0_CLK] = &nss_cc_nssnoc_ubi32_axi0_clk.clkr, ++ [NSS_CC_NSSNOC_UBI32_INT0_AHB_CLK] = ++ &nss_cc_nssnoc_ubi32_int0_ahb_clk.clkr, ++ [NSS_CC_NSSNOC_UBI32_NC_AXI0_1_CLK] = ++ &nss_cc_nssnoc_ubi32_nc_axi0_1_clk.clkr, ++ [NSS_CC_NSSNOC_UBI32_NC_AXI0_CLK] = ++ &nss_cc_nssnoc_ubi32_nc_axi0_clk.clkr, ++ [NSS_CC_PORT1_MAC_CLK] = &nss_cc_port1_mac_clk.clkr, ++ [NSS_CC_PORT1_RX_CLK] = &nss_cc_port1_rx_clk.clkr, ++ [NSS_CC_PORT1_RX_CLK_SRC] = &nss_cc_port1_rx_clk_src.clkr, ++ [NSS_CC_PORT1_RX_DIV_CLK_SRC] = &nss_cc_port1_rx_div_clk_src.clkr, ++ [NSS_CC_PORT1_TX_CLK] = &nss_cc_port1_tx_clk.clkr, ++ [NSS_CC_PORT1_TX_CLK_SRC] = &nss_cc_port1_tx_clk_src.clkr, ++ [NSS_CC_PORT1_TX_DIV_CLK_SRC] = &nss_cc_port1_tx_div_clk_src.clkr, ++ [NSS_CC_PORT2_MAC_CLK] = &nss_cc_port2_mac_clk.clkr, ++ [NSS_CC_PORT2_RX_CLK] = &nss_cc_port2_rx_clk.clkr, ++ [NSS_CC_PORT2_RX_CLK_SRC] = &nss_cc_port2_rx_clk_src.clkr, ++ [NSS_CC_PORT2_RX_DIV_CLK_SRC] = &nss_cc_port2_rx_div_clk_src.clkr, ++ [NSS_CC_PORT2_TX_CLK] = &nss_cc_port2_tx_clk.clkr, ++ [NSS_CC_PORT2_TX_CLK_SRC] = &nss_cc_port2_tx_clk_src.clkr, ++ [NSS_CC_PORT2_TX_DIV_CLK_SRC] = &nss_cc_port2_tx_div_clk_src.clkr, ++ [NSS_CC_PORT3_MAC_CLK] = &nss_cc_port3_mac_clk.clkr, ++ [NSS_CC_PORT3_RX_CLK] = &nss_cc_port3_rx_clk.clkr, ++ [NSS_CC_PORT3_RX_CLK_SRC] = &nss_cc_port3_rx_clk_src.clkr, ++ [NSS_CC_PORT3_RX_DIV_CLK_SRC] = &nss_cc_port3_rx_div_clk_src.clkr, ++ [NSS_CC_PORT3_TX_CLK] = &nss_cc_port3_tx_clk.clkr, ++ [NSS_CC_PORT3_TX_CLK_SRC] = &nss_cc_port3_tx_clk_src.clkr, ++ [NSS_CC_PORT3_TX_DIV_CLK_SRC] = &nss_cc_port3_tx_div_clk_src.clkr, ++ [NSS_CC_PORT4_MAC_CLK] = &nss_cc_port4_mac_clk.clkr, ++ [NSS_CC_PORT4_RX_CLK] = &nss_cc_port4_rx_clk.clkr, ++ [NSS_CC_PORT4_RX_CLK_SRC] = &nss_cc_port4_rx_clk_src.clkr, ++ [NSS_CC_PORT4_RX_DIV_CLK_SRC] = &nss_cc_port4_rx_div_clk_src.clkr, ++ [NSS_CC_PORT4_TX_CLK] = &nss_cc_port4_tx_clk.clkr, ++ [NSS_CC_PORT4_TX_CLK_SRC] = &nss_cc_port4_tx_clk_src.clkr, ++ [NSS_CC_PORT4_TX_DIV_CLK_SRC] = &nss_cc_port4_tx_div_clk_src.clkr, ++ [NSS_CC_PORT5_MAC_CLK] = &nss_cc_port5_mac_clk.clkr, ++ [NSS_CC_PORT5_RX_CLK] = &nss_cc_port5_rx_clk.clkr, ++ [NSS_CC_PORT5_RX_CLK_SRC] = &nss_cc_port5_rx_clk_src.clkr, ++ [NSS_CC_PORT5_RX_DIV_CLK_SRC] = &nss_cc_port5_rx_div_clk_src.clkr, ++ [NSS_CC_PORT5_TX_CLK] = &nss_cc_port5_tx_clk.clkr, ++ [NSS_CC_PORT5_TX_CLK_SRC] = &nss_cc_port5_tx_clk_src.clkr, ++ [NSS_CC_PORT5_TX_DIV_CLK_SRC] = &nss_cc_port5_tx_div_clk_src.clkr, ++ [NSS_CC_PORT6_MAC_CLK] = &nss_cc_port6_mac_clk.clkr, ++ [NSS_CC_PORT6_RX_CLK] = &nss_cc_port6_rx_clk.clkr, ++ [NSS_CC_PORT6_RX_CLK_SRC] = &nss_cc_port6_rx_clk_src.clkr, ++ [NSS_CC_PORT6_RX_DIV_CLK_SRC] = &nss_cc_port6_rx_div_clk_src.clkr, ++ [NSS_CC_PORT6_TX_CLK] = &nss_cc_port6_tx_clk.clkr, ++ [NSS_CC_PORT6_TX_CLK_SRC] = &nss_cc_port6_tx_clk_src.clkr, ++ [NSS_CC_PORT6_TX_DIV_CLK_SRC] = &nss_cc_port6_tx_div_clk_src.clkr, ++ [NSS_CC_PPE_CLK_SRC] = &nss_cc_ppe_clk_src.clkr, ++ [NSS_CC_PPE_EDMA_CFG_CLK] = &nss_cc_ppe_edma_cfg_clk.clkr, ++ [NSS_CC_PPE_EDMA_CLK] = &nss_cc_ppe_edma_clk.clkr, ++ [NSS_CC_PPE_SWITCH_BTQ_CLK] = &nss_cc_ppe_switch_btq_clk.clkr, ++ [NSS_CC_PPE_SWITCH_CFG_CLK] = &nss_cc_ppe_switch_cfg_clk.clkr, ++ [NSS_CC_PPE_SWITCH_CLK] = &nss_cc_ppe_switch_clk.clkr, ++ [NSS_CC_PPE_SWITCH_IPE_CLK] = &nss_cc_ppe_switch_ipe_clk.clkr, ++ [NSS_CC_UBI0_CLK_SRC] = &nss_cc_ubi0_clk_src.clkr, ++ [NSS_CC_UBI0_DIV_CLK_SRC] = &nss_cc_ubi0_div_clk_src.clkr, ++ [NSS_CC_UBI1_CLK_SRC] = &nss_cc_ubi1_clk_src.clkr, ++ [NSS_CC_UBI1_DIV_CLK_SRC] = &nss_cc_ubi1_div_clk_src.clkr, ++ [NSS_CC_UBI2_CLK_SRC] = &nss_cc_ubi2_clk_src.clkr, ++ [NSS_CC_UBI2_DIV_CLK_SRC] = &nss_cc_ubi2_div_clk_src.clkr, ++ [NSS_CC_UBI32_AHB0_CLK] = &nss_cc_ubi32_ahb0_clk.clkr, ++ [NSS_CC_UBI32_AHB1_CLK] = &nss_cc_ubi32_ahb1_clk.clkr, ++ [NSS_CC_UBI32_AHB2_CLK] = &nss_cc_ubi32_ahb2_clk.clkr, ++ [NSS_CC_UBI32_AHB3_CLK] = &nss_cc_ubi32_ahb3_clk.clkr, ++ [NSS_CC_UBI32_AXI0_CLK] = &nss_cc_ubi32_axi0_clk.clkr, ++ [NSS_CC_UBI32_AXI1_CLK] = &nss_cc_ubi32_axi1_clk.clkr, ++ [NSS_CC_UBI32_AXI2_CLK] = &nss_cc_ubi32_axi2_clk.clkr, ++ [NSS_CC_UBI32_AXI3_CLK] = &nss_cc_ubi32_axi3_clk.clkr, ++ [NSS_CC_UBI32_CORE0_CLK] = &nss_cc_ubi32_core0_clk.clkr, ++ [NSS_CC_UBI32_CORE1_CLK] = &nss_cc_ubi32_core1_clk.clkr, ++ [NSS_CC_UBI32_CORE2_CLK] = &nss_cc_ubi32_core2_clk.clkr, ++ [NSS_CC_UBI32_CORE3_CLK] = &nss_cc_ubi32_core3_clk.clkr, ++ [NSS_CC_UBI32_INTR0_AHB_CLK] = &nss_cc_ubi32_intr0_ahb_clk.clkr, ++ [NSS_CC_UBI32_INTR1_AHB_CLK] = &nss_cc_ubi32_intr1_ahb_clk.clkr, ++ [NSS_CC_UBI32_INTR2_AHB_CLK] = &nss_cc_ubi32_intr2_ahb_clk.clkr, ++ [NSS_CC_UBI32_INTR3_AHB_CLK] = &nss_cc_ubi32_intr3_ahb_clk.clkr, ++ [NSS_CC_UBI32_NC_AXI0_CLK] = &nss_cc_ubi32_nc_axi0_clk.clkr, ++ [NSS_CC_UBI32_NC_AXI1_CLK] = &nss_cc_ubi32_nc_axi1_clk.clkr, ++ [NSS_CC_UBI32_NC_AXI2_CLK] = &nss_cc_ubi32_nc_axi2_clk.clkr, ++ [NSS_CC_UBI32_NC_AXI3_CLK] = &nss_cc_ubi32_nc_axi3_clk.clkr, ++ [NSS_CC_UBI32_UTCM0_CLK] = &nss_cc_ubi32_utcm0_clk.clkr, ++ [NSS_CC_UBI32_UTCM1_CLK] = &nss_cc_ubi32_utcm1_clk.clkr, ++ [NSS_CC_UBI32_UTCM2_CLK] = &nss_cc_ubi32_utcm2_clk.clkr, ++ [NSS_CC_UBI32_UTCM3_CLK] = &nss_cc_ubi32_utcm3_clk.clkr, ++ [NSS_CC_UBI3_CLK_SRC] = &nss_cc_ubi3_clk_src.clkr, ++ [NSS_CC_UBI3_DIV_CLK_SRC] = &nss_cc_ubi3_div_clk_src.clkr, ++ [NSS_CC_UBI_AXI_CLK_SRC] = &nss_cc_ubi_axi_clk_src.clkr, ++ [NSS_CC_UBI_NC_AXI_BFDCD_CLK_SRC] = ++ &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr, ++ [NSS_CC_UNIPHY_PORT1_RX_CLK] = &nss_cc_uniphy_port1_rx_clk.clkr, ++ [NSS_CC_UNIPHY_PORT1_TX_CLK] = &nss_cc_uniphy_port1_tx_clk.clkr, ++ [NSS_CC_UNIPHY_PORT2_RX_CLK] = &nss_cc_uniphy_port2_rx_clk.clkr, ++ [NSS_CC_UNIPHY_PORT2_TX_CLK] = &nss_cc_uniphy_port2_tx_clk.clkr, ++ [NSS_CC_UNIPHY_PORT3_RX_CLK] = &nss_cc_uniphy_port3_rx_clk.clkr, ++ [NSS_CC_UNIPHY_PORT3_TX_CLK] = &nss_cc_uniphy_port3_tx_clk.clkr, ++ [NSS_CC_UNIPHY_PORT4_RX_CLK] = &nss_cc_uniphy_port4_rx_clk.clkr, ++ [NSS_CC_UNIPHY_PORT4_TX_CLK] = &nss_cc_uniphy_port4_tx_clk.clkr, ++ [NSS_CC_UNIPHY_PORT5_RX_CLK] = &nss_cc_uniphy_port5_rx_clk.clkr, ++ [NSS_CC_UNIPHY_PORT5_TX_CLK] = &nss_cc_uniphy_port5_tx_clk.clkr, ++ [NSS_CC_UNIPHY_PORT6_RX_CLK] = &nss_cc_uniphy_port6_rx_clk.clkr, ++ [NSS_CC_UNIPHY_PORT6_TX_CLK] = &nss_cc_uniphy_port6_tx_clk.clkr, ++ [NSS_CC_XGMAC0_PTP_REF_CLK] = &nss_cc_xgmac0_ptp_ref_clk.clkr, ++ [NSS_CC_XGMAC0_PTP_REF_DIV_CLK_SRC] = ++ &nss_cc_xgmac0_ptp_ref_div_clk_src.clkr, ++ [NSS_CC_XGMAC1_PTP_REF_CLK] = &nss_cc_xgmac1_ptp_ref_clk.clkr, ++ [NSS_CC_XGMAC1_PTP_REF_DIV_CLK_SRC] = ++ &nss_cc_xgmac1_ptp_ref_div_clk_src.clkr, ++ [NSS_CC_XGMAC2_PTP_REF_CLK] = &nss_cc_xgmac2_ptp_ref_clk.clkr, ++ [NSS_CC_XGMAC2_PTP_REF_DIV_CLK_SRC] = ++ &nss_cc_xgmac2_ptp_ref_div_clk_src.clkr, ++ [NSS_CC_XGMAC3_PTP_REF_CLK] = &nss_cc_xgmac3_ptp_ref_clk.clkr, ++ [NSS_CC_XGMAC3_PTP_REF_DIV_CLK_SRC] = ++ &nss_cc_xgmac3_ptp_ref_div_clk_src.clkr, ++ [NSS_CC_XGMAC4_PTP_REF_CLK] = &nss_cc_xgmac4_ptp_ref_clk.clkr, ++ [NSS_CC_XGMAC4_PTP_REF_DIV_CLK_SRC] = ++ &nss_cc_xgmac4_ptp_ref_div_clk_src.clkr, ++ [NSS_CC_XGMAC5_PTP_REF_CLK] = &nss_cc_xgmac5_ptp_ref_clk.clkr, ++ [NSS_CC_XGMAC5_PTP_REF_DIV_CLK_SRC] = ++ &nss_cc_xgmac5_ptp_ref_div_clk_src.clkr, ++ [UBI32_PLL] = &ubi32_pll.clkr, ++ [UBI32_PLL_MAIN] = &ubi32_pll_main.clkr, ++}; ++ ++static const struct qcom_reset_map nss_cc_ipq9574_resets[] = { ++ [NSS_CC_CE_BCR] = { 0x28400, 0 }, ++ [NSS_CC_CLC_BCR] = { 0x28600, 0 }, ++ [NSS_CC_EIP197_BCR] = { 0x16004, 0 }, ++ [NSS_CC_HAQ_BCR] = { 0x28300, 0 }, ++ [NSS_CC_IMEM_BCR] = { 0xe004, 0 }, ++ [NSS_CC_MAC_BCR] = { 0x28100, 0 }, ++ [NSS_CC_PPE_BCR] = { 0x28200, 0 }, ++ [NSS_CC_UBI_BCR] = { 0x28700, 0 }, ++ [NSS_CC_UNIPHY_BCR] = { 0x28900, 0 }, ++ [UBI3_CLKRST_CLAMP_ENABLE] = { 0x28a04, 9 }, ++ [UBI3_CORE_CLAMP_ENABLE] = { 0x28a04, 8 }, ++ [UBI2_CLKRST_CLAMP_ENABLE] = { 0x28a04, 7 }, ++ [UBI2_CORE_CLAMP_ENABLE] = { 0x28a04, 6 }, ++ [UBI1_CLKRST_CLAMP_ENABLE] = { 0x28a04, 5 }, ++ [UBI1_CORE_CLAMP_ENABLE] = { 0x28a04, 4 }, ++ [UBI0_CLKRST_CLAMP_ENABLE] = { 0x28a04, 3 }, ++ [UBI0_CORE_CLAMP_ENABLE] = { 0x28a04, 2 }, ++ [NSSNOC_NSS_CSR_ARES] = { 0x28a04, 1 }, ++ [NSS_CSR_ARES] = { 0x28a04, 0 }, ++ [PPE_BTQ_ARES] = { 0x28a08, 20 }, ++ [PPE_IPE_ARES] = { 0x28a08, 19 }, ++ [PPE_ARES] = { 0x28a08, 18 }, ++ [PPE_CFG_ARES] = { 0x28a08, 17 }, ++ [PPE_EDMA_ARES] = { 0x28a08, 16 }, ++ [PPE_EDMA_CFG_ARES] = { 0x28a08, 15 }, ++ [CRY_PPE_ARES] = { 0x28a08, 14 }, ++ [NSSNOC_PPE_ARES] = { 0x28a08, 13 }, ++ [NSSNOC_PPE_CFG_ARES] = { 0x28a08, 12 }, ++ [PORT1_MAC_ARES] = { 0x28a08, 11 }, ++ [PORT2_MAC_ARES] = { 0x28a08, 10 }, ++ [PORT3_MAC_ARES] = { 0x28a08, 9 }, ++ [PORT4_MAC_ARES] = { 0x28a08, 8 }, ++ [PORT5_MAC_ARES] = { 0x28a08, 7 }, ++ [PORT6_MAC_ARES] = { 0x28a08, 6 }, ++ [XGMAC0_PTP_REF_ARES] = { 0x28a08, 5 }, ++ [XGMAC1_PTP_REF_ARES] = { 0x28a08, 4 }, ++ [XGMAC2_PTP_REF_ARES] = { 0x28a08, 3 }, ++ [XGMAC3_PTP_REF_ARES] = { 0x28a08, 2 }, ++ [XGMAC4_PTP_REF_ARES] = { 0x28a08, 1 }, ++ [XGMAC5_PTP_REF_ARES] = { 0x28a08, 0 }, ++ [HAQ_AHB_ARES] = { 0x28a0c, 3 }, ++ [HAQ_AXI_ARES] = { 0x28a0c, 2 }, ++ [NSSNOC_HAQ_AHB_ARES] = { 0x28a0c, 1 }, ++ [NSSNOC_HAQ_AXI_ARES] = { 0x28a0c, 0 }, ++ [CE_APB_ARES] = { 0x28a10, 3 }, ++ [CE_AXI_ARES] = { 0x28a10, 2 }, ++ [NSSNOC_CE_APB_ARES] = { 0x28a10, 1 }, ++ [NSSNOC_CE_AXI_ARES] = { 0x28a10, 0 }, ++ [CRYPTO_ARES] = { 0x28a14, 1 }, ++ [NSSNOC_CRYPTO_ARES] = { 0x28a14, 0 }, ++ [NSSNOC_NC_AXI0_1_ARES] = { 0x28a1c, 28 }, ++ [UBI0_CORE_ARES] = { 0x28a1c, 27 }, ++ [UBI1_CORE_ARES] = { 0x28a1c, 26 }, ++ [UBI2_CORE_ARES] = { 0x28a1c, 25 }, ++ [UBI3_CORE_ARES] = { 0x28a1c, 24 }, ++ [NC_AXI0_ARES] = { 0x28a1c, 23 }, ++ [UTCM0_ARES] = { 0x28a1c, 22 }, ++ [NC_AXI1_ARES] = { 0x28a1c, 21 }, ++ [UTCM1_ARES] = { 0x28a1c, 20 }, ++ [NC_AXI2_ARES] = { 0x28a1c, 19 }, ++ [UTCM2_ARES] = { 0x28a1c, 18 }, ++ [NC_AXI3_ARES] = { 0x28a1c, 17 }, ++ [UTCM3_ARES] = { 0x28a1c, 16 }, ++ [NSSNOC_NC_AXI0_ARES] = { 0x28a1c, 15 }, ++ [AHB0_ARES] = { 0x28a1c, 14 }, ++ [INTR0_AHB_ARES] = { 0x28a1c, 13 }, ++ [AHB1_ARES] = { 0x28a1c, 12 }, ++ [INTR1_AHB_ARES] = { 0x28a1c, 11 }, ++ [AHB2_ARES] = { 0x28a1c, 10 }, ++ [INTR2_AHB_ARES] = { 0x28a1c, 9 }, ++ [AHB3_ARES] = { 0x28a1c, 8 }, ++ [INTR3_AHB_ARES] = { 0x28a1c, 7 }, ++ [NSSNOC_AHB0_ARES] = { 0x28a1c, 6 }, ++ [NSSNOC_INT0_AHB_ARES] = { 0x28a1c, 5 }, ++ [AXI0_ARES] = { 0x28a1c, 4 }, ++ [AXI1_ARES] = { 0x28a1c, 3 }, ++ [AXI2_ARES] = { 0x28a1c, 2 }, ++ [AXI3_ARES] = { 0x28a1c, 1 }, ++ [NSSNOC_AXI0_ARES] = { 0x28a1c, 0 }, ++ [IMEM_QSB_ARES] = { 0x28a20, 3 }, ++ [NSSNOC_IMEM_QSB_ARES] = { 0x28a20, 2 }, ++ [IMEM_AHB_ARES] = { 0x28a20, 1 }, ++ [NSSNOC_IMEM_AHB_ARES] = { 0x28a20, 0 }, ++ [UNIPHY_PORT1_RX_ARES] = { 0x28a24, 23 }, ++ [UNIPHY_PORT1_TX_ARES] = { 0x28a24, 22 }, ++ [UNIPHY_PORT2_RX_ARES] = { 0x28a24, 21 }, ++ [UNIPHY_PORT2_TX_ARES] = { 0x28a24, 20 }, ++ [UNIPHY_PORT3_RX_ARES] = { 0x28a24, 19 }, ++ [UNIPHY_PORT3_TX_ARES] = { 0x28a24, 18 }, ++ [UNIPHY_PORT4_RX_ARES] = { 0x28a24, 17 }, ++ [UNIPHY_PORT4_TX_ARES] = { 0x28a24, 16 }, ++ [UNIPHY_PORT5_RX_ARES] = { 0x28a24, 15 }, ++ [UNIPHY_PORT5_TX_ARES] = { 0x28a24, 14 }, ++ [UNIPHY_PORT6_RX_ARES] = { 0x28a24, 13 }, ++ [UNIPHY_PORT6_TX_ARES] = { 0x28a24, 12 }, ++ [PORT1_RX_ARES] = { 0x28a24, 11 }, ++ [PORT1_TX_ARES] = { 0x28a24, 10 }, ++ [PORT2_RX_ARES] = { 0x28a24, 9 }, ++ [PORT2_TX_ARES] = { 0x28a24, 8 }, ++ [PORT3_RX_ARES] = { 0x28a24, 7 }, ++ [PORT3_TX_ARES] = { 0x28a24, 6 }, ++ [PORT4_RX_ARES] = { 0x28a24, 5 }, ++ [PORT4_TX_ARES] = { 0x28a24, 4 }, ++ [PORT5_RX_ARES] = { 0x28a24, 3 }, ++ [PORT5_TX_ARES] = { 0x28a24, 2 }, ++ [PORT6_RX_ARES] = { 0x28a24, 1 }, ++ [PORT6_TX_ARES] = { 0x28a24, 0 }, ++ [PPE_FULL_RESET] = { .reg = 0x28a08, .bitmask = GENMASK(20, 17) }, ++ [UNIPHY0_SOFT_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(23, 14) }, ++ [UNIPHY1_SOFT_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(15, 14) }, ++ [UNIPHY2_SOFT_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(13, 12) }, ++ [UNIPHY_PORT1_ARES] = { .reg = 0x28a24, .bitmask = GENMASK(23, 22) }, ++ [UNIPHY_PORT2_ARES] = { .reg = 0x28a24, .bitmask = GENMASK(21, 20) }, ++ [UNIPHY_PORT3_ARES] = { .reg = 0x28a24, .bitmask = GENMASK(19, 18) }, ++ [UNIPHY_PORT4_ARES] = { .reg = 0x28a24, .bitmask = GENMASK(17, 16) }, ++ [UNIPHY_PORT5_ARES] = { .reg = 0x28a24, .bitmask = GENMASK(15, 14) }, ++ [UNIPHY_PORT6_ARES] = { .reg = 0x28a24, .bitmask = GENMASK(13, 12) }, ++ [NSSPORT1_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(11, 10) }, ++ [NSSPORT2_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(9, 8) }, ++ [NSSPORT3_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(7, 6) }, ++ [NSSPORT4_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(5, 4) }, ++ [NSSPORT5_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(3, 2) }, ++ [NSSPORT6_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(1, 0) }, ++ [EDMA_HW_RESET] = { .reg = 0x28a08, .bitmask = GENMASK(16, 15) }, ++}; ++ ++static const struct regmap_config nss_cc_ipq9574_regmap_config = { ++ .reg_bits = 32, ++ .reg_stride = 4, ++ .val_bits = 32, ++ .max_register = 0x28a34, ++ .fast_io = true, ++}; ++ ++static struct qcom_icc_hws_data icc_ipq9574_nss_hws[] = { ++ { MASTER_NSSNOC_PPE, SLAVE_NSSNOC_PPE, NSS_CC_NSSNOC_PPE_CLK }, ++ { MASTER_NSSNOC_PPE_CFG, SLAVE_NSSNOC_PPE_CFG, NSS_CC_NSSNOC_PPE_CFG_CLK }, ++ { MASTER_NSSNOC_NSS_CSR, SLAVE_NSSNOC_NSS_CSR, NSS_CC_NSSNOC_NSS_CSR_CLK }, ++ { MASTER_NSSNOC_IMEM_QSB, SLAVE_NSSNOC_IMEM_QSB, NSS_CC_NSSNOC_IMEM_QSB_CLK }, ++ { MASTER_NSSNOC_IMEM_AHB, SLAVE_NSSNOC_IMEM_AHB, NSS_CC_NSSNOC_IMEM_AHB_CLK }, ++}; ++ ++#define IPQ_NSSCC_ID (9574 * 2) /* some unique value */ ++ ++static const struct qcom_cc_desc nss_cc_ipq9574_desc = { ++ .config = &nss_cc_ipq9574_regmap_config, ++ .clks = nss_cc_ipq9574_clocks, ++ .num_clks = ARRAY_SIZE(nss_cc_ipq9574_clocks), ++ .resets = nss_cc_ipq9574_resets, ++ .num_resets = ARRAY_SIZE(nss_cc_ipq9574_resets), ++ .icc_hws = icc_ipq9574_nss_hws, ++ .num_icc_hws = ARRAY_SIZE(icc_ipq9574_nss_hws), ++ .icc_first_node_id = IPQ_NSSCC_ID, ++}; ++ ++static const struct dev_pm_ops nss_cc_ipq9574_pm_ops = { ++ SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) ++}; ++ ++static const struct of_device_id nss_cc_ipq9574_match_table[] = { ++ { .compatible = "qcom,ipq9574-nsscc" }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, nss_cc_ipq9574_match_table); ++ ++static int nss_cc_ipq9574_probe(struct platform_device *pdev) ++{ ++ struct regmap *regmap; ++ int ret; ++ ++ ret = devm_pm_runtime_enable(&pdev->dev); ++ if (ret) ++ return dev_err_probe(&pdev->dev, ret, "Fail to enable runtime PM\n"); ++ ++ ret = devm_pm_clk_create(&pdev->dev); ++ if (ret) ++ return dev_err_probe(&pdev->dev, ret, "Fail to create PM clock\n"); ++ ++ ret = pm_clk_add(&pdev->dev, "bus"); ++ if (ret) ++ return dev_err_probe(&pdev->dev, ret, "Fail to add bus clock\n"); ++ ++ ret = pm_runtime_resume_and_get(&pdev->dev); ++ if (ret) ++ return dev_err_probe(&pdev->dev, ret, "Fail to resume\n"); ++ ++ regmap = qcom_cc_map(pdev, &nss_cc_ipq9574_desc); ++ if (IS_ERR(regmap)) { ++ pm_runtime_put(&pdev->dev); ++ return dev_err_probe(&pdev->dev, PTR_ERR(regmap), ++ "Fail to map clock controller registers\n"); ++ } ++ ++ clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config); ++ ++ ret = qcom_cc_really_probe(&pdev->dev, &nss_cc_ipq9574_desc, regmap); ++ pm_runtime_put(&pdev->dev); ++ ++ return ret; ++} ++ ++static struct platform_driver nss_cc_ipq9574_driver = { ++ .probe = nss_cc_ipq9574_probe, ++ .driver = { ++ .name = "qcom,nsscc-ipq9574", ++ .of_match_table = nss_cc_ipq9574_match_table, ++ .pm = &nss_cc_ipq9574_pm_ops, ++ .sync_state = icc_sync_state, ++ }, ++}; ++ ++module_platform_driver(nss_cc_ipq9574_driver); ++ ++MODULE_DESCRIPTION("Qualcomm Technologies, Inc. NSSCC IPQ9574 Driver"); ++MODULE_LICENSE("GPL"); diff --git a/target/linux/qualcommbe/patches-6.12/0022-v6.15-arm64-defconfig-Build-NSS-Clock-Controller-dri.patch b/target/linux/qualcommbe/patches-6.12/0022-v6.15-arm64-defconfig-Build-NSS-Clock-Controller-dri.patch new file mode 100644 index 00000000000..1f4dfd210c2 --- /dev/null +++ b/target/linux/qualcommbe/patches-6.12/0022-v6.15-arm64-defconfig-Build-NSS-Clock-Controller-dri.patch @@ -0,0 +1,29 @@ +From 8f1b61ea1cb98735aa15a8875d729c21a2169fb9 Mon Sep 17 00:00:00 2001 +From: Devi Priya +Date: Thu, 13 Mar 2025 16:33:59 +0530 +Subject: [PATCH 22/22] v6.15: arm64: defconfig: Build NSS Clock Controller + driver for IPQ9574 + +NSSCC driver is needed to enable the ethernet interfaces present +in RDP433 based on IPQ9574. Since this is not necessary for bootup +enabling it as a module. + +Reviewed-by: Krzysztof Kozlowski +Signed-off-by: Devi Priya +Signed-off-by: Manikanta Mylavarapu +Link: https://lore.kernel.org/r/20250313110359.242491-7-quic_mmanikan@quicinc.com +Signed-off-by: Bjorn Andersson +--- + arch/arm64/configs/defconfig | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm64/configs/defconfig ++++ b/arch/arm64/configs/defconfig +@@ -1313,6 +1313,7 @@ CONFIG_IPQ_GCC_5332=y + CONFIG_IPQ_GCC_6018=y + CONFIG_IPQ_GCC_8074=y + CONFIG_IPQ_GCC_9574=y ++CONFIG_IPQ_NSSCC_9574=m + CONFIG_MSM_GCC_8916=y + CONFIG_MSM_MMCC_8994=m + CONFIG_MSM_GCC_8994=y