From: Richard Henderson Date: Wed, 7 Jan 2026 01:15:24 +0000 (+1100) Subject: tcg: Remove INDEX_op_brcond2_i32 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=e3601d2cfca21c68ee4efb27ce5f0b0aa1d8c758;p=thirdparty%2Fqemu.git tcg: Remove INDEX_op_brcond2_i32 This opcode was exclusively for 32-bit hosts. Reviewed-by: Thomas Huth Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- diff --git a/docs/devel/tcg-ops.rst b/docs/devel/tcg-ops.rst index f26b837a30..10d5edb4ca 100644 --- a/docs/devel/tcg-ops.rst +++ b/docs/devel/tcg-ops.rst @@ -705,11 +705,6 @@ They are emitted as needed by inline functions within ``tcg-op.h``. .. list-table:: - * - brcond2_i32 *t0_low*, *t0_high*, *t1_low*, *t1_high*, *cond*, *label* - - - | Similar to brcond, except that the 64-bit values *t0* and *t1* - are formed from two 32-bit arguments. - * - setcond2_i32 *dest*, *t1_low*, *t1_high*, *t2_low*, *t2_high*, *cond* - | Similar to setcond, except that the 64-bit values *t1* and *t2* are @@ -940,7 +935,7 @@ The target word size (``TCG_TARGET_REG_BITS``) is expected to be 32 bit or On a 32 bit target, all 64 bit operations are converted to 32 bits. A few specific operations must be implemented to allow it -(see brcond2_i32, setcond2_i32). +(see setcond2_i32). On a 64 bit target, the values are transferred between 32 and 64-bit registers using the following ops: diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index e988edd93a..55283af326 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -103,7 +103,6 @@ DEF(subb1o, 1, 2, 0, TCG_OPF_INT | TCG_OPF_CARRY_OUT) DEF(subbi, 1, 2, 0, TCG_OPF_INT | TCG_OPF_CARRY_IN) DEF(subbio, 1, 2, 0, TCG_OPF_INT | TCG_OPF_CARRY_IN | TCG_OPF_CARRY_OUT) -DEF(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH) DEF(setcond2_i32, 1, 4, 1, 0) /* size changing ops */ diff --git a/tcg/optimize.c b/tcg/optimize.c index 5ae26e4a10..a544c055b8 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -1597,102 +1597,6 @@ static bool fold_brcond(OptContext *ctx, TCGOp *op) return true; } -static bool fold_brcond2(OptContext *ctx, TCGOp *op) -{ - TCGCond cond; - TCGArg label; - int i, inv = 0; - - i = do_constant_folding_cond2(ctx, op, &op->args[0]); - cond = op->args[4]; - label = op->args[5]; - if (i >= 0) { - goto do_brcond_const; - } - - switch (cond) { - case TCG_COND_LT: - case TCG_COND_GE: - /* - * Simplify LT/GE comparisons vs zero to a single compare - * vs the high word of the input. - */ - if (arg_is_const_val(op->args[2], 0) && - arg_is_const_val(op->args[3], 0)) { - goto do_brcond_high; - } - break; - - case TCG_COND_NE: - inv = 1; - QEMU_FALLTHROUGH; - case TCG_COND_EQ: - /* - * Simplify EQ/NE comparisons where one of the pairs - * can be simplified. - */ - i = do_constant_folding_cond(TCG_TYPE_I32, op->args[0], - op->args[2], cond); - switch (i ^ inv) { - case 0: - goto do_brcond_const; - case 1: - goto do_brcond_high; - } - - i = do_constant_folding_cond(TCG_TYPE_I32, op->args[1], - op->args[3], cond); - switch (i ^ inv) { - case 0: - goto do_brcond_const; - case 1: - goto do_brcond_low; - } - break; - - case TCG_COND_TSTEQ: - case TCG_COND_TSTNE: - if (arg_is_const_val(op->args[2], 0)) { - goto do_brcond_high; - } - if (arg_is_const_val(op->args[3], 0)) { - goto do_brcond_low; - } - break; - - default: - break; - - do_brcond_low: - op->opc = INDEX_op_brcond; - op->args[1] = op->args[2]; - op->args[2] = cond; - op->args[3] = label; - return fold_brcond(ctx, op); - - do_brcond_high: - op->opc = INDEX_op_brcond; - op->args[0] = op->args[1]; - op->args[1] = op->args[3]; - op->args[2] = cond; - op->args[3] = label; - return fold_brcond(ctx, op); - - do_brcond_const: - if (i == 0) { - tcg_op_remove(ctx->tcg, op); - return true; - } - op->opc = INDEX_op_br; - op->args[0] = label; - finish_ebb(ctx); - return true; - } - - finish_bb(ctx); - return true; -} - static bool fold_bswap(OptContext *ctx, TCGOp *op) { uint64_t z_mask, o_mask, s_mask; @@ -3163,9 +3067,6 @@ void tcg_optimize(TCGContext *s) case INDEX_op_brcond: done = fold_brcond(&ctx, op); break; - case INDEX_op_brcond2_i32: - done = fold_brcond2(&ctx, op); - break; case INDEX_op_bswap16: case INDEX_op_bswap32: case INDEX_op_bswap64: diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index ab7b409be6..61f6fd9095 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -265,14 +265,6 @@ static void DNI tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5), a6); } -static TCGOp * DNI tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, - TCGv_i32 a3, TCGv_i32 a4, - TCGArg a5, TCGArg a6) -{ - return tcg_gen_op6(opc, TCG_TYPE_I32, tcgv_i32_arg(a1), tcgv_i32_arg(a2), - tcgv_i32_arg(a3), tcgv_i32_arg(a4), a5, a6); -} - /* Generic ops. */ void gen_set_label(TCGLabel *l) @@ -1873,33 +1865,15 @@ void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, TCGLabel *l) if (cond == TCG_COND_ALWAYS) { tcg_gen_br(l); } else if (cond != TCG_COND_NEVER) { - TCGOp *op; - if (TCG_TARGET_REG_BITS == 32) { - op = tcg_gen_op6ii_i32(INDEX_op_brcond2_i32, TCGV_LOW(arg1), - TCGV_HIGH(arg1), TCGV_LOW(arg2), - TCGV_HIGH(arg2), cond, label_arg(l)); - } else { - op = tcg_gen_op4ii_i64(INDEX_op_brcond, arg1, arg2, cond, - label_arg(l)); - } + TCGOp *op = tcg_gen_op4ii_i64(INDEX_op_brcond, arg1, arg2, cond, + label_arg(l)); add_as_label_use(l, op); } } void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, TCGLabel *l) { - if (TCG_TARGET_REG_BITS == 64) { - tcg_gen_brcond_i64(cond, arg1, tcg_constant_i64(arg2), l); - } else if (cond == TCG_COND_ALWAYS) { - tcg_gen_br(l); - } else if (cond != TCG_COND_NEVER) { - TCGOp *op = tcg_gen_op6ii_i32(INDEX_op_brcond2_i32, - TCGV_LOW(arg1), TCGV_HIGH(arg1), - tcg_constant_i32(arg2), - tcg_constant_i32(arg2 >> 32), - cond, label_arg(l)); - add_as_label_use(l, op); - } + tcg_gen_brcond_i64(cond, arg1, tcg_constant_i64(arg2), l); } void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret, diff --git a/tcg/tcg.c b/tcg/tcg.c index fbf09f5c82..0521767c46 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1010,13 +1010,6 @@ typedef struct TCGOutOpBrcond { TCGReg a1, tcg_target_long a2, TCGLabel *label); } TCGOutOpBrcond; -typedef struct TCGOutOpBrcond2 { - TCGOutOp base; - void (*out)(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, - TCGArg bl, bool const_bl, - TCGArg bh, bool const_bh, TCGLabel *l); -} TCGOutOpBrcond2; - typedef struct TCGOutOpBswap { TCGOutOp base; void (*out_rr)(TCGContext *s, TCGType type, @@ -1248,7 +1241,6 @@ static const TCGOutOp * const all_outop[NB_OPS] = { [INDEX_op_goto_ptr] = &outop_goto_ptr, #if TCG_TARGET_REG_BITS == 32 - OUTOP(INDEX_op_brcond2_i32, TCGOutOpBrcond2, outop_brcond2), OUTOP(INDEX_op_setcond2_i32, TCGOutOpSetcond2, outop_setcond2), #else OUTOP(INDEX_op_bswap64, TCGOutOpUnary, outop_bswap64), @@ -2490,7 +2482,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, unsigned flags) case INDEX_op_xor: return has_type; - case INDEX_op_brcond2_i32: case INDEX_op_setcond2_i32: return TCG_TARGET_REG_BITS == 32; @@ -3022,7 +3013,6 @@ void tcg_dump_ops(TCGContext *s, FILE *f, bool have_prefs) case INDEX_op_setcond: case INDEX_op_negsetcond: case INDEX_op_movcond: - case INDEX_op_brcond2_i32: case INDEX_op_setcond2_i32: case INDEX_op_cmp_vec: case INDEX_op_cmpsel_vec: @@ -3106,7 +3096,6 @@ void tcg_dump_ops(TCGContext *s, FILE *f, bool have_prefs) case INDEX_op_set_label: case INDEX_op_br: case INDEX_op_brcond: - case INDEX_op_brcond2_i32: col += ne_fprintf(f, "%s$L%d", k ? "," : "", arg_label(op->args[k])->id); i++, k++; @@ -3563,9 +3552,6 @@ void tcg_op_remove(TCGContext *s, TCGOp *op) case INDEX_op_brcond: remove_label_use(op, 3); break; - case INDEX_op_brcond2_i32: - remove_label_use(op, 5); - break; default: break; } @@ -3664,9 +3650,6 @@ static void move_label_uses(TCGLabel *to, TCGLabel *from) case INDEX_op_brcond: op->args[3] = label_arg(to); break; - case INDEX_op_brcond2_i32: - op->args[5] = label_arg(to); - break; default: g_assert_not_reached(); } @@ -5285,9 +5268,6 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) case INDEX_op_cmp_vec: op_cond = op->args[3]; break; - case INDEX_op_brcond2_i32: - op_cond = op->args[4]; - break; case INDEX_op_movcond: case INDEX_op_setcond2_i32: case INDEX_op_cmpsel_vec: @@ -5890,19 +5870,6 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) break; #if TCG_TARGET_REG_BITS == 32 - case INDEX_op_brcond2_i32: - { - const TCGOutOpBrcond2 *out = &outop_brcond2; - TCGCond cond = new_args[4]; - TCGLabel *label = arg_label(new_args[5]); - - tcg_debug_assert(!const_args[0]); - tcg_debug_assert(!const_args[1]); - out->out(s, cond, new_args[0], new_args[1], - new_args[2], const_args[2], - new_args[3], const_args[3], label); - } - break; case INDEX_op_setcond2_i32: { const TCGOutOpSetcond2 *out = &outop_setcond2; @@ -5915,7 +5882,6 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) } break; #else - case INDEX_op_brcond2_i32: case INDEX_op_setcond2_i32: g_assert_not_reached(); #endif diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 532f87262c..1756ffc59c 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -1047,23 +1047,6 @@ static const TCGOutOpMovcond outop_movcond = { .out = tgen_movcond, }; -static void tgen_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, - TCGArg bl, bool const_bl, - TCGArg bh, bool const_bh, TCGLabel *l) -{ - tcg_out_op_rrrrrc(s, INDEX_op_setcond2_i32, TCG_REG_TMP, - al, ah, bl, bh, cond); - tcg_out_op_rl(s, INDEX_op_brcond, TCG_REG_TMP, l); -} - -#if TCG_TARGET_REG_BITS != 32 -__attribute__((unused)) -#endif -static const TCGOutOpBrcond2 outop_brcond2 = { - .base.static_constraint = C_O0_I4(r, r, r, r), - .out = tgen_brcond2, -}; - static void tgen_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, TCGReg al, TCGReg ah, TCGArg bl, bool const_bl,