From: Mukul Joshi Date: Thu, 27 Mar 2025 21:17:06 +0000 (-0400) Subject: drm/amdgpu: Fix SHMEM alignment mode for GFX 12.1.0 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=e3b8d8cc8c60db6c2be1251664da68b3e021a672;p=thirdparty%2Fkernel%2Flinux.git drm/amdgpu: Fix SHMEM alignment mode for GFX 12.1.0 Alignment mode in SHMEM config register is only a single bit value on GFX 12.1.0 instead of 2 bits in previous asics. Add a new enum and use the correct value of SHMEM alignment mode when programming the SHMEM config register. Signed-off-by: Mukul Joshi Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c index 3080aecc83414..023a8a1114a33 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c @@ -52,9 +52,10 @@ MODULE_FIRMWARE("amdgpu/gc_12_1_0_mec.bin"); MODULE_FIRMWARE("amdgpu/gc_12_1_0_rlc.bin"); +#define SH_MEM_ALIGNMENT_MODE_UNALIGNED_GFX12_1_0 0x00000001 #define DEFAULT_SH_MEM_CONFIG \ ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ - (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ + (SH_MEM_ALIGNMENT_MODE_UNALIGNED_GFX12_1_0 << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) static void gfx_v12_1_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v12_1.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v12_1.c index db7675c1498de..e4ec7190fea14 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v12_1.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v12_1.c @@ -24,7 +24,7 @@ #include "kfd_device_queue_manager.h" #include "gc/gc_12_1_0_sh_mask.h" -#include "soc24_enum.h" +#include "soc_v1_0_enum.h" static int update_qpd_v12_1(struct device_queue_manager *dqm, struct qcm_process_device *qpd); diff --git a/drivers/gpu/drm/amd/include/soc_v1_0_enum.h b/drivers/gpu/drm/amd/include/soc_v1_0_enum.h index 5a0963eaf3b9a..2a910785334db 100644 --- a/drivers/gpu/drm/amd/include/soc_v1_0_enum.h +++ b/drivers/gpu/drm/amd/include/soc_v1_0_enum.h @@ -30,4 +30,9 @@ typedef enum MTYPE { MTYPE_UC = 0x00000003, } MTYPE; +typedef enum SH_MEM_ALIGNMENT_MODE { + SH_MEM_ALIGNMENT_MODE_DWORD = 0x00000000, + SH_MEM_ALIGNMENT_MODE_UNALIGNED = 0x00000001, +} SH_MEM_ALIGNMENT_MODE; + #endif