From: Pan Li <pan2.li@intel.com>
Date: Sun, 18 May 2025 09:07:37 +0000 (+0800)
Subject: RISC-V: Add test for vec_duplicate + vrsub.vv combine case 0 with GR2VR cost 1
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=e604b48288b41402539d22531cfd96003382aff8;p=thirdparty%2Fgcc.git

RISC-V: Add test for vec_duplicate + vrsub.vv combine case 0 with GR2VR cost 1

Add asm dump check test for vec_duplicate + vrsub.vv combine to vrsub.vx

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c: Add vrsub asm
	dump check.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c: Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>
---

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
index 49e9957cf15..c55eaaac278 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_0(int16_t, +, add)
 DEF_VX_BINARY_CASE_0(int16_t, -, sub)
+DEF_VX_BINARY_REVERSE_CASE_0(int16_t, -, rsub);
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
+/* { dg-final { scan-assembler-not {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
index 869f9fd7e24..0a0258ccfee 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_0(int32_t, +, add)
 DEF_VX_BINARY_CASE_0(int32_t, -, sub)
+DEF_VX_BINARY_REVERSE_CASE_0(int32_t, -, rsub);
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
+/* { dg-final { scan-assembler-not {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
index 6ba71431997..4956315ee14 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_0(int64_t, +, add)
 DEF_VX_BINARY_CASE_0(int64_t, -, sub)
+DEF_VX_BINARY_REVERSE_CASE_0(int64_t, -, rsub);
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
+/* { dg-final { scan-assembler-not {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
index 128a279dbb2..c1fa3b605d7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_0(int8_t, +, add)
 DEF_VX_BINARY_CASE_0(int8_t, -, sub)
+DEF_VX_BINARY_REVERSE_CASE_0(int8_t, -, rsub);
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
+/* { dg-final { scan-assembler-not {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
index a2a35ccd8f1..5dca3850240 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_0(uint16_t, +, add)
 DEF_VX_BINARY_CASE_0(uint16_t, -, sub)
+DEF_VX_BINARY_REVERSE_CASE_0(uint16_t, -, rsub);
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
+/* { dg-final { scan-assembler-not {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
index bd89bfa6fd0..4460fc06d00 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_0(uint32_t, +, add)
 DEF_VX_BINARY_CASE_0(uint32_t, -, sub)
+DEF_VX_BINARY_REVERSE_CASE_0(uint32_t, -, rsub);
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
+/* { dg-final { scan-assembler-not {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
index 134efe88bf3..e8282c3d219 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_0(uint64_t, +, add)
 DEF_VX_BINARY_CASE_0(uint64_t, -, sub)
+DEF_VX_BINARY_REVERSE_CASE_0(int64_t, -, rsub);
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
+/* { dg-final { scan-assembler-not {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
index b1c7c5d09f6..7b744f1b460 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_0(uint8_t, +, add)
 DEF_VX_BINARY_CASE_0(uint8_t, -, sub)
+DEF_VX_BINARY_REVERSE_CASE_0(uint8_t, -, rsub);
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
+/* { dg-final { scan-assembler-not {vrsub.vx} } } */