From: Julian Seward <jseward@acm.org>
Date: Fri, 20 Apr 2012 10:42:24 +0000 (+0000)
Subject: Changes to make t-chaining work on ppc64-linux.  More fun than a
X-Git-Tag: svn/VALGRIND_3_8_1^2~182^2~3
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=e6e65cc82f98802385e16670211dc1b316ad4536;p=thirdparty%2Fvalgrind.git

Changes to make t-chaining work on ppc64-linux.  More fun than a
bathtub full of ferrets.  (VEX side)


git-svn-id: svn://svn.valgrind.org/vex/branches/TCHAIN@2292
---

diff --git a/VEX/priv/host_ppc_defs.c b/VEX/priv/host_ppc_defs.c
index 5e8399025d..263f5bc534 100644
--- a/VEX/priv/host_ppc_defs.c
+++ b/VEX/priv/host_ppc_defs.c
@@ -1850,10 +1850,10 @@ void ppPPCInstr ( PPCInstr* i, Bool mode64 )
 
    case Pin_ProfInc:
       if (mode64) {
-         vex_printf("(profInc) imm64 r30,$NotKnownYet;");
+         vex_printf("(profInc) imm64-fixed5 r30,$NotKnownYet; ");
          vex_printf("ld r29,(r30); addi r29,r29,1; std r29,(r30)");
       } else {
-         vex_printf("(profInc) imm32 r30,$NotKnownYet;");
+         vex_printf("(profInc) imm32-fixed2 r30,$NotKnownYet; ");
          vex_printf("lwz r29,4(r30); addic. r29,r29,1; stw r29,4(r30)");
          vex_printf("lwz r29,0(r30); addze r29,r29; stw r29,0(r30)");
       }
@@ -3629,6 +3629,7 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_profInc,
          //case Ijk_Sys_int128:  trcval = VEX_TRC_JMP_SYS_INT128;  break;
          //case Ijk_Yield:       trcval = VEX_TRC_JMP_YIELD;       break;
          case Ijk_EmWarn:      trcval = VEX_TRC_JMP_EMWARN;      break;
+         case Ijk_EmFail:      trcval = VEX_TRC_JMP_EMFAIL;      break;
          //case Ijk_MapFail:     trcval = VEX_TRC_JMP_MAPFAIL;     break;
          case Ijk_NoDecode:    trcval = VEX_TRC_JMP_NODECODE;    break;
          case Ijk_TInval:      trcval = VEX_TRC_JMP_TINVAL;      break;
@@ -4620,14 +4621,14 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_profInc,
             64-bit:
               imm64-exactly r30, 0x6555655565556555
               ld      r29, 0(r30)
-              add     r29, r29, 1
+              addi    r29, r29, 1
               std     r29, 0(r30)
       */
       if (mode64) {
          p = mkLoadImm_EXACTLY2or5(
                 p, /*r*/30, 0x6555655565556555ULL, True/*mode64*/);
          p = emit32(p, 0xEBBE0000);
-         p = emit32(p, 0x7FBD0A14);
+         p = emit32(p, 0x3BBD0001);
          p = emit32(p, 0xFBBE0000);
       } else {
          p = mkLoadImm_EXACTLY2or5(
@@ -4774,7 +4775,7 @@ VexInvalRange patchProfInc_PPC ( void*  place_to_patch,
       vassert(isLoadImm_EXACTLY2or5(p, /*r*/30,
                                     0x6555655565556555ULL, True/*mode64*/));
       vassert(fetch32(p + 20) == 0xEBBE0000);
-      vassert(fetch32(p + 24) == 0x7FBD0A14);
+      vassert(fetch32(p + 24) == 0x3BBD0001);
       vassert(fetch32(p + 28) == 0xFBBE0000);
       p = mkLoadImm_EXACTLY2or5(p, /*r*/30,
                                 Ptr_to_ULong(location_of_counter),
diff --git a/VEX/priv/host_ppc_isel.c b/VEX/priv/host_ppc_isel.c
index 2778dc7c11..4f28bdfa26 100644
--- a/VEX/priv/host_ppc_isel.c
+++ b/VEX/priv/host_ppc_isel.c
@@ -4600,6 +4600,7 @@ static void iselStmt ( ISelEnv* env, IRStmt* stmt )
          //case Ijk_MapFail:
          //case Ijk_SigSEGV: case Ijk_TInval: case Ijk_EmWarn:
          case Ijk_NoDecode: case Ijk_SigBUS: case Ijk_SigTRAP:
+         case Ijk_EmFail:
          {
             HReg r = iselWordExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst));
             addInstr(env, PPCInstr_XAssisted(r, amCIA, cc,
diff --git a/VEX/priv/main_main.c b/VEX/priv/main_main.c
index feaf459589..7419ceddab 100644
--- a/VEX/priv/main_main.c
+++ b/VEX/priv/main_main.c
@@ -838,6 +838,10 @@ VexInvalRange LibVEX_Chain ( VexArch arch_host,
          return chainXDirect_PPC(place_to_chain,
                                  disp_cp_chain_me_EXPECTED,
                                  place_to_jump_to, False/*!mode64*/);
+      case VexArchPPC64:
+         return chainXDirect_PPC(place_to_chain,
+                                 disp_cp_chain_me_EXPECTED,
+                                 place_to_jump_to, True/*mode64*/);
       default:
          vassert(0);
    }
@@ -867,6 +871,10 @@ VexInvalRange LibVEX_UnChain ( VexArch arch_host,
          return unchainXDirect_PPC(place_to_unchain,
                                    place_to_jump_to_EXPECTED,
                                    disp_cp_chain_me, False/*!mode64*/);
+      case VexArchPPC64:
+         return unchainXDirect_PPC(place_to_unchain,
+                                   place_to_jump_to_EXPECTED,
+                                   disp_cp_chain_me, True/*mode64*/);
       default:
          vassert(0);
    }
@@ -891,6 +899,7 @@ Int LibVEX_evCheckSzB ( VexArch arch_host )
          case VexArchS390X:
             cached = evCheckSzB_S390(); break;
          case VexArchPPC32:
+         case VexArchPPC64:
             cached = evCheckSzB_PPC(); break;
          default:
             vassert(0);
@@ -916,6 +925,9 @@ VexInvalRange LibVEX_PatchProfInc ( VexArch arch_host,
       case VexArchPPC32:
          return patchProfInc_PPC(place_to_patch,
                                  location_of_counter, False/*!mode64*/);
+      case VexArchPPC64:
+         return patchProfInc_PPC(place_to_patch,
+                                 location_of_counter, True/*mode64*/);
       default:
          vassert(0);
    }